Fujitsu Corporation

Noriyasu Nakayama

Nobukazu Koizumi

Hisao Nakashima

Koji Nakamuta

Tomoki Kato

Hiroyuki Hieda

Takeshi Hoshida

Takahito Tanimura

Kazuhiko Hatae

Naoki Yuzawa

Satoshi Hiramoto

Kosuke Komaki

Yuji Obana

A digital coherent receiving apparatus includes a first oscillator for outputting a local light signal of a fixed frequency, a hybrid unit mixing the local light signal with a light signal received by a receiver, a second oscillator for outputting a sampling signal of a sampling frequency, a converter for converting the mixed light signal into digital signal synchronizing with the sampling signal, a waveform adjuster for adjusting a waveform distortion of the converted digital signal, a phase adjustor for adjusting a phase of the digital signal adjusted by the waveform adjustor, a demodulator for demodulating the digital signal adjusted by the phase adjuster, and a phase detector for detecting a phase of the digital signal adjusted by the phase adjuster, and a control signal output unit for outputting a frequency control signal on the basis of the detected phase signal to the second oscillator.

Digital coherent receiving apparatus

An adaptive equalizer includes a finite impulse response filter with a predetermined number of taps; and a tap coefficient adaptive controller having a register to hold tap coefficients for the filter, a weighted center calculator to calculate a weighted center of the tap coefficients, and a tap coefficient shifter to shift the tap coefficients based on a calculation result of the weighted center. During an initial training period, the tap coefficient shifter shifts the tap coefficients on a symbol data basis such that a difference between the calculated weighted center of the tap coefficients and a tap center defined by the number of taps is minimized.

Adaptive equalizer, optical receiver, and tap coefficient correcting method

An ALC processing unit to adjust the signal level of outputs from an adaptive equalizer to a target value is provided in a stage later than the adaptive equalizer and earlier than a frequency offset estimation/compensation unit in an optical digital coherent receiver. The ALC processing unit generates a histogram that counts the number of samples for discrete monitored values corresponding to amplitude values of outputs from the adaptive equalizer, and determines a level adjustment coefficient that is to be multiplied by an output from the adaptive equalizer so as to multiply the determined coefficient by the output from the adaptive equalizer so that the monitored value of the peak value of the histogram is the target value.

Optical digital coherent receiver

A simulation method includes obtaining an execution log generated while a predetermined processing is executed by simulating a series of operations in a test model that is a modeled version of a test target device by causing a predetermined processing to be executed in the test model, extracting a processing unit log constituted by a predetermined processing unit from the execution log obtained in the obtaining, and simulating an operation in which processing corresponding to the processing unit log extracted in the extracting is executed in a test model in which a part of function of the test target device is modified, the operation being simulated on the basis of a setting condition set by a user.

Simulation method and simulation apparatus

The present invention relates to a technique for executing performance evaluation simulation of a system to be implemented by software or hardware. A simulation apparatus includes a first acquisition section for executing existing tentative software to acquire a first execution log, a division section for dividing the first execution log into a plurality of basic processing units, a basic processing execution log production section for modifying some of the plural basic processing units to produce a basic processing execution log to be used for simulation, and a simulation execution section for inputting the basic processing execution log to a hardware model to execute the simulation to acquire information required for the performance evaluation.

Method and an apparatus for executing simulation for system performance evaluation

A redundant logic circuit detection method includes storing unit-logic-circuit information, waveform data and a limiting condition in a storage section. The unit-logic-circuit information indicates a plurality of unit-logic-circuits synthesized based on logic design information. The waveform data indicates a logic simulation result with respect to the plurality of unit-logic-circuits. The limiting condition defines a comparison condition of the waveform data. The method selects a first unit-logic-circuit from the plurality of unit-logic-circuits. The method detects a second unit-logic-circuit having a substantially identical sequence of the waveform data to the first unit-logic-circuit based on the limiting condition. The method outputs the first unit-logic-circuit and the second unit-logic-circuit as redundant circuit information.

Redundant logic circuit detection method and device and computer-readable recording medium

A performance evaluation simulation apparatus divides a process into basic process units based on an execution log, calculates a throughput of each basic process unit from information held in the execution log, changes an arrangement structure so that a basic process unit with the calculated throughput exceeding a predetermined threshold is disposed in a hardware model, and performs a performance evaluation simulation on the hardware model and a software model to generate statistical information on which performance evaluation is based.

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Kawasaki, Japan

Noriyasu Nakayama