Hitachi, Ltd.

Noriyasu Ido

Tatsumi Yamauchi

Hiromichi Yamada

Keiji Kojima

Fumio Murabayashi

Shunichi Torii

Yoshikazu Kiyoshige

Takahiro Nishiyama

Takashi Hotta

Makoto Hanawa

Kenji Kaneko

Hideo Sawamoto

Eiki Kamada

A floating-point arithmetic processing apparatus has a circuit for generating a limit value for normalization shift by subtracting an exponent of the minimum value of a normalized number from a value of an exponent of an intermediate result, and a circuit for generating, as a normalization shift number, smaller one of a shift number necessary for making the mantissa of the intermediate result a normalized number and the limit value for normalization shift. The floating-point arithmetic processing apparatus further has a circuit having a circuit for detecting a condition for overflow before the rounding process and a circuit for generating a value in the case of overflow, so that a predetermined value is delivered as a final result only when the overflow condition is detected before the rounding process but in the other case, a result obtained by performing the normalization process and the rounding process is delivered. When no overflow takes place before the rounding process but overflow occurs after the rounding process, the result obtained by performing the normalization process and the rounding process is delivered as a final result.

Floating-point arithmetic processing apparatus

To offer a floating-point addition/subtraction processing apparatus and a method thereof, capable of shortening the computation time, the floating-point calculation processing apparatus includes an approximate shift mount predicting unit for predicting a shift amount for normalization by using the input floating-point data to be addition/subtraction processed within an error of 1 bit, a shift error detecting unit for detecting a difference between the predicted shift amount and a correct shift amount, and an bit shifter for correcting a result, obtained by normalization using the predicted shift amount, by the detected difference of the two shift amounts, wherein a round-off determination and a shift amount calculation are processed in parallel before a normalization shift processing is executed.

Floating-point addition/substraction processing apparatus and method

A pass transistor type selector circuit comprises a control signal supplying circuit for supplying a pair of control signals of opposite phases to the respective gate electrodes of a pair of nMOS transistors of a selecting circuit. The control signal supplying circuit includes a control signal interrupting means which operates in synchronism with a clock signal so as to selectively interrupt the supply of the control signals to the signal selecting circuit while the clock signal is low level. The control signal interrupting means is provided with a discharging means for discharging high-level one of the gate electrodes of the nMOS transistors of the signal selecting circuit while the clock signal is low level. The discharging means comprises two nMOS transistors, each connected between the respective gate electrodes of the nMOS transistors of the signal selecting circuit and a grounding terminal.

Pass transistor type selector circuit and digital logic circuit

Associative keys and retrieve outputs corresponding thereto are registered to an associative memory in a vector data conversion apparatus. Conversion vector data stored in the main storage and comprising vector elements of the same type of an associative key is sequentially read out for each vector element and is inputted to a comparator, which then compares the vector element with the associative keys beforehand registered to the associative memory so as to determine whether or not a matching condition exists therebetween. When the comparator detects the matching condition, a retrieve output corresponding to the matched associative key is read out from the associative memory and is stored in the main storage. While the conversion vector data is sequentially read out for each vector in this manner, the retrieve output data is sequentially stored in the main storage so as to generate the converted vector data comprising the retrieve output data as vector elements. A user identifier may also be inputted as a compare element together with the associative key, thereby preventing an erroneous data conversion from taking place even when a plurality of users share the vector data conversion apparatus.

Data processor with associative memory storing vector elements for

A vector to be processed consisting of a plurality of partial vectors each having a variable number of vector elements and a key vector consisting of a fixed number of vector elements are vector-processed while the vector elements of those vectors are sequentially read out. A vector processor has a punctuation detection circuit for detecting a punctuation between the partial vectors in the vector to be processed. The reading of the key vector is restored to the reading of the start vector element in accordance with the detection signal from the punctuation detection circuit.

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Hadano, Japan

Noriyasu Ido