Kabushiki Kaisha Toshiba

Kioxia Corporation

Noriya Sakamoto

Akihisa Fujimoto

Atsushi Kondo

Atsushi Hirota

Masahiro Yamada

Toshitada Saito

Hiroshi Isozaki

Kiyoyuki Kawai

Taku Nishiyama

Seijiro Yasuki

Katsuyoshi Watanabe

Michihiro Fukushima

Natsuki Koshiro

Tatsuya Ishikawa

Jun Kanai

Hiroyuki Aizu

Hiroyuki Nagata

Tatsuya Uehara

Yasuhiro Fujiyoshi

Susumu Komatsu

Eiichiro Tomonaga

Chihoko Shigeta

Takayasu Tsuchiuchi

Tsukasa Kudo

Jun Kano

Shuuichi Shibaoka

According to one embodiment, there is provided a memory card including a first surface, a second surface, and 1to Nterminal groups. The first surface includes first to Nrows, where N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1to Nterminal groups are placed in the first to Nrows. The 1terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kterminal group, where K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.

Memory card with multiple modes, and host device corresponding to the memory card

According to one embodiment, a semiconductor memory device includes a housing and terminals. The housing has a first end edge extending in a first direction and a second end edge opposite to the first end edge. The terminals include signal terminals and include first terminals, second terminals, and third terminals. The first terminals are arranged in the first direction at a position close to the first end edge. The second terminals are arranged in the first direction with intervals at a position closer to the first end edge than the second end edge. The first plurality of terminals are closer to the first end edge than the second plurality of terminals are. The third terminals are arranged in the first direction with intervals at a position closer to the second end edge than the first end edge.

Semiconductor memory device

A memory card includes a first surface, a second surface, and 1to Nterminal groups. The first surface includes first to Nrows, wherein N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1to Nterminal groups are placed in the first to Nrows. The 1terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kterminal group, wherein K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.

According to an embodiment, a tuner unit, a managing unit, a private code verifying unit, an application origin verifying unit, and a device operation command processing unit. The tuner unit is configured to perform a decoding process of a broadcast program and program related information from broadcasting waves. The managing unit is configured to store a private code on a device-by-device basis. The private code verifying unit is configured to verify whether the private code obtained from an information manipulation device matches with the stored private code. The application origin verifying unit is configured to determine whether first origin information that has been received matches with second origin information of the application being executed. The device operation command processing unit is configured to allow execution of the device operation command when the first origin information and the second origin information match and when the private codes match.

Information output device, information manipulation device, and computer program product

In at least one embodiment, a reception apparatus includes a discrimination data receiver configured to receive discrimination data that is transmitted from outside the reception apparatus and that has been associated with display information to be displayed; and an output controller configured to control output of the display information to two or more display screens according to the discrimination data.

Reception apparatus, reception method and external apparatus linking system

An information output apparatus has a first interface to receive an equipment operational signal from a short-range wireless communication apparatus, a second interface to receive broadcast wave data based on the equipment operational signal, a third interface to transmit the equipment operational signal to an information generating apparatus, a fourth interface to receive video data transmitted from the information generating apparatus, a fifth interface to receive a control command transmitted from the information generating apparatus in response to the equipment operational signal transmitted from the third interface part, an information superimposing part to transmit the equipment operational signal from the third interface part to the information generating apparatus and then to superimpose video data updated by the information generating apparatus and received from the fourth interface part with the broadcast wave data to display the superimposed data on a display part.

Information output apparatus, information processing system and information processing method

A receiver for the digital broadcasts with which an appropriate copy regulation is executed for a temporal recording. Regarding the temporal recording of the programs of the digital broadcasts, either of the signals of the system including at least the signals, which represent 'recording permitted' or 'recording prohibited', is received as the temporal record control data and the record control is executed in accordance with the temporal record control data to execute the temporal recording of the received broadcast program or not to execute the temporal recording.

Digital broadcast transmitter, receiver and method of receiving thereof

A demultiplexing/GOP head detecting section detects a PCR value, while a recording/reproduction control section records a video or audio packet in a bit stream file and records information on the number of packets every PCR value and GOP. In reproduction, a reproduction position corresponding to a shift time is judged on the basis of information on the number of packets at every PCR value and GOP. This improves the shifting and returning speeds to time shift reproduction.

Recording/reproducing apparatus, video data recording apparatus, recording method, reproducing method

A digital broadcast receiving device includes a first processor for extracting added information, a storage device for storing the added information, and a second processor having a low power consumption mode and a normal power mode, for effecting the circuit control for the watching and listening operation according to a preset program and the added information. The first processor informs the second processor that the added information is extracted, the second processor changes the mode thereof to the normal power mode when it is informed from the first processor that the added information is extracted while it is set in the low power consumption mode in the standby state, writes the added information extracted by the first processor into the storage device, and changes the mode thereof into the low power consumption mode after completion of the write operation.

Digital broadcast receiving device

Digital broadcast receiving terminal apparatus which receives multi-channel digital broadcast signals to record the huge capacity without deteriorating the quality of signals and to visualize the digital broadcasting. The outputs form the error correction decoding circus 4 are applied to the TS processor 12 via the switches SW 1 and SW 2, at the same time they are applied to the recording program selector 11. The recording program selector 11 applies the encoded data of the predetermined program to the digital interface 13, the digital interface 13 inputs and outputs the encoded data through bus in the IEEE1394 specification for example. Thus, the encoded data are applied to the external equipment and recorded as they are, and the degradation of the quality can be prevented. The switches SW 1 and SW 2 changes the receiving signals and the outputs from the digital interface 13 and applies them to the TS processor 12. The TS processor 12 depacketizes the input encoded data. Therefore, the image reproduction based on the receiving signals or the outputs from the external equipment can be carried out.

Digital broadcast receiving terminal apparatus

Communication processing system with multiple data layers for digital

A PLL circuit for use in a digital broadcasting receiver includes a receiver for receiving a bit stream containing program clock references (PCRs) transmitted from a broadcast station. The PCRs correspond to a frequency and phase of a transmitter system clock. The circuit also contains an oscillator for generating receiver system clocks, a counter responsive to the system clocks, and a connection to allow the bit stream to flow from the receiver to the oscillator. A controller controls the counter based on differences between the PCRs in the bit stream and the counter output. A load control means successively loads the PCRs on the counter in their order of transmission to lock the frequency and phase of the receiver system clock provided from the oscillator with the frequency and phase of the transmitter system clock. This arrangement allows quick adjustment of the receiver system clock frequency and phase by removing the influence of the insertion intervals of the PCRs in the bit stream when making the adjustment.

PLL circuit and method

A system capable of performing compatible transmitting and receiving processes, regardless of whether a TV signal on the transmission side is a high-resolution signal or a low-resolution signal or whether the reception side includes a high-resolution display unit or a low-resolution display unit. On the transmission side, a frequency division circuit divides a high-resolution TV signal into signals in a plurality of frequency bands. The signals in each frequency band are converted into signals of a horizontal and vertical low band (a low-resolution TV signal band). The converted signals are coded by coding units, which transmit the coded signals. On the reception side, the coded signals multiplexed on the transmission side are separated and decoded at decoding units. A frequency synthesizing circuit restores the frequency bands of the decoded signals to the original bands. Then, the resulting signals are displayed with a high resolution. A low-resolution signal is coded and then transmitted. The coded signal is decoded on the reception side. The decoded signal is interpolated at an interpolation circuit. The interpolated signal is then displayed on a high-resolution display unit.

Growing community of inventors

Ome, Japan

Noriya Sakamoto