Nec Corporation

Renesas Electronics Corporation

Fuji Jukogyo Kabushiki Kaisha

The University of Tokyo

Nec Electronics Corporation

Noritsugu Nakamura

Takao Toi

Taro Fujii

Toru Awashima

Masato Motomura

Koichiro Furuta

Toshimichi Ogisu

Yoshikazu Yabe

Kenichiro Anjo

Nobuo Takeda

Yoshinosuke Kato

Yoshiharu Aimoto

Hirokazu Kami

Toshiro Kitaoka

Yoshiyuki Miyazawa

A behavioral synthesis apparatus includes a determination unit that determines whether or not a loop description should be converted into a pipeline, and a synthesis unit that performs behavioral synthesis while setting a stricter delay constraint for a loop description that is converted into a pipeline than a loop description that is not converted into a pipeline.

Behavioral synthesis apparatus, behavioral synthesis method, data processing system including behavioral synthesis apparatus, and non-transitory computer readable medium storing behavioral synthesis program

A behavioral synthesis device include a profile unit that implements an electronic circuit at a reconfigurable hardware based on a first register transfer level description generated by a behavioral synthesis unit, actuates the implemented electronic circuit, and causes the electric circuit to output profile information from the actuated electronic circuit; and an optimizer that generates optimization information for optimizing a behavioral synthesis carried out by the behavioral synthesis unit based on the profile information that the profile unit causes the electric circuit to output, and outputs the generated optimization information to the behavioral synthesis unit, wherein the behavioral synthesis unit acquires a first behavioral level description, and subjects the acquired first behavioral level description to behavioral synthesis and generates the second register transfer level description based on the optimization information outputted by the optimizer.

Behavioral synthesis device, behavioral synthesis method, and computer program product

A behavioral synthesis apparatus includes a acquisition unit, a scheduling unit and a generation unit. The acquisition unit acquires a behavioral level description describing an operation of a semiconductor integrated circuit. The scheduling unit separates the acquired behavioral level description into N stage descriptions, and makes a schedule in such a way that input/output operations and computations among the N stage descriptions are pipelined. The generation unit generates a register transfer level description based on the N stage descriptions and a result of scheduling performed by the scheduling unit in such a way as to form stage circuits respectively corresponding to the N stage descriptions and a state control circuit which controls possible 2N&#x2212;1 stage control states of the semiconductor integrated circuit. The generation unit generates the register transfer level description in such a way as to inhibit the operation of a stage circuit which need not be operated.

Behavioral synthesis apparatus, behavioral synthesis method, and computer readable recording medium

A multiplicity of processor elements that are arranged in rows and columns individually execute data processing in accordance with instruction codes that are individually set as data and supply event data as output. A state control unit is composed of a plurality of units that successively switch the instruction codes of the multiplicity of processor elements in accordance with a computer program and the event data, these state control units communicating with each other to realize linked operation as necessary. An event distributing means distributes event data to this plurality of state control units that intercommunicate to realize linked operation, whereby the plurality of state control units can realize linked operation to control a large-scale state transition.

Array-type processor having plural processor elements controlled by a state control unit

Disclosed is an impact detection system including: an optical fiber including a plurality of sensor sections to reflect light, a wavelength band of the reflected light vibrates depending on an elastic wave propagating through a subject to be inspected; a light source to input light into the optical fiber; optical filters each connected to an output terminal of the optical fiber; and an arithmetic processing unit to detect the impact from output values of sensor sections, wherein the wavelength bands of the sensor sections in the optical fiber are distributed such that the vibration bands caused by the impact to be detected do not overlap with each other, and a pass band of the optical filter corresponding to one of the sensor sections is distributed in the vibration band caused by the detection object, and is distributed in both sides of a center of the wavelength band of the one sensor section.

Impact detection system using an optical fiber sensor

Disclosed an impact detection system including: three or more optical fiber sensors disposed respectively in different positions, the sensors not being in alignment with one another, in which the sensors each includes a core portion to have a grating portion formed therein, the grating portion has a plurality of gratings; light source; two or more optical filters having different pass bands to one another to an output light of one of the optical fiber sensors; and an arithmetic processing apparatus to perform arithmetic processing of output values of the three or more optical fiber sensors through the optical filters so as to specify a position on the subject where an impact is loaded, the output values being obtained when the impact is loaded on the subject.

Impact detection system with three or more optical fiber sensors

A multiplicity of processor elements, which both individually execute data processing in accordance with instruction codes that have been set as data and for which mutual connection relations are switch-controlled, are arranged in matrix form, and the instruction codes of this multiplicity of processor elements are successively switched by a state control unit. The state control units are composed of a plurality of units that intercommunicate to realize linked operation, and the multiplicity of processor elements is divided into a number of element areas that corresponds to the number of state control units. The plurality of state control units are arranged for each of the plurality of element areas and are connected to the processor elements, whereby the plurality of state control units can individually control a plurality of small-scale state transitions, or the plurality of state control units can cooperate to control a single large-scale state transition.

Array-type processor having state control units controlling a plurality of processor elements arranged in a matrix

An object code for sequentially switching contexts of processing circuits arrayed in a matrix in a parallel operation apparatus is generated from a general source code descriptive of operation of the parallel operation apparatus. A Data Flow Graph (DFG) is generated from the source code descriptive of operation of the parallel operation apparatus according to limiting conditions, registered in advance, representing a physical structure, etc. of the parallel operation apparatus, and scheduled in a Control Data Flow Graph (CDFG). An Register Transfer Level (RTL) description is generated from the CDFG, converting a finite-state machine into an object code and converting a data path into a net list. An object code of the processing circuits is generated in each context from the net list.

Data processing apparatus and method for generating the data of an object program for a parallel operation apparatus

A SRAM has a plurality of four-transistor/no-load memory cells each operating in a precharge mode for maintaining stored data based on off-leak currents of MOSFETs. The SRAM has a reference voltage generator, an impedance converter, a plurality of word line drivers, and a plurality of word lines each extending along a row of the memory cells.

SRAM operating with a reduced power dissipation

A semiconductor memory device includes a pair of data lines, a precharging and equalizing circuit, a setting circuit and a data write circuit. The precharging and equalizing circuit is provided between the data lines to equally precharge the data lines to a first voltage in response to a precharge and equalize signal. The setting circuit is provided between the data lines to set one of the precharged data lines to a second voltage in response to data signals. The second voltage is lower than the first voltage. Also, a data Is written to a memory cell based on the second voltage of the one precharged data line and the first voltage of the other precharged data line. The data write circuit supplies the data signals to the setting circuit based on the data.

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Tokyo, Japan

Noritsugu Nakamura