Ricoh Company, Ltd.

Mitsubishi Denki Kabushiki Kaisha

Norio Yoshida

Yoshio Inoue

Tetsuo Hikawa

Yuichi Ando

Koichi Sogawa

Satoru Taji

Yoshiaki Fukui

Masao Kiyohara

Yasunori Kishimoto

Tsuneki Suzuki

A simulator for simulating operations of a logical circuit has as its object the provision of a simulator capable of detailed timing error checking without impairing the simulation executing speed. A timing check primitive adding circuit, based on circuit information indicating electronic devices and loop circuits selected for timing error checking, outputs circuit information with simulation control data for controlling the simulation of only the selected devices or selected loop circuits. A timing error detection circuit and a timing error cause analyzing circuit grasp changes in test pattern input and output signals of a selected device and perform detailed timing error checking.

Simulator for simulating circuit operation

There is disclosed a simulator having timing error detecting from input and output signal level changes. Different timing error verifications are carried out for respective elements. In similar constructions, different test rule error verifications are also carried out for the respective elements as a function of the contents of a test rule check value definition file.

Simulator for conducting timing analysis of a circuit

A semiconductor memory device comprising a substrate, a longitudinal source diffusion layer for a plurality of memory transistor source regions continuously formed on the substrate, and a longitudinal drain diffusion layer for a plurality of memory transistor drain regions continuously formed on the substrate in parallel to the source diffusion layer. A word line is formed crossing over the diffusion layers. And an electrically insulating film is interposed between the word line and the diffusion layers. The insulating film is thicker than a gate oxide film formed between the diffusion layers.

Semiconductor memory device

A semiconductor memory device is highly integrated by a combination of planer cell structure with the trench etching technique. Trenches are formed on a substrate in parallel with each other, and diffused layers are on sidewalls of the trenches to provide bit lines. Gates oxide layers are formed on the bottoms of trenches and on surfaces of the substrate between adjacent two trenches, and silicon oxide layers thicker than the gate oxide layers are on the bit lines. Word lines are formed in band in parallel with each other in a direction to cross the trenches perpendicularly thereto. Channel regions are defined in portions of word lines on the bottoms of trenches and on the surfaces of substrate crossed thereby. Ion implantation is conducted into each memory transistor according to data to determine a ROM code, to set a threshold value therein.

Semiconductor memory device and production process thereof

The circuit simulator stores an information representing a relation between the level transition on an output signal of each element in an object circuit and an input terminal to which a test pattern is applied. When a timing error occurs, an error message outputted based upon the information facilitates to narrow down the range of subjects to be analyzed for seeking the cause of the error, whereby the cause of a timing error can be easily cleared up.

Circuit simulator

The etch rate of phosphosilicate glass becomes lowered as boron ions are implanted therein. In accordance with the principle of the present invention, boron ions are implanted into a phosphosilicate glass film selectively in location or concentration and the thus boron-implanted phosphosilicate glass film is etched by an etchant, for example buffered hydrofluoric acid solution, to etch an intended portion of the phosphosilcate glass film preferentially thereby defining a hole, such as a contact hole, or substantially flat surface.

Growing community of inventors

Hyogo, Japan

Norio Yoshida