Fujitsu Corporation

Nippon Telegraph and Telephone Public Corporation

Shiseido Company, Limited

Norio Ueno

Toru Matsuyama

Tadashi Ikeuchi

Tadao Inoue

Norio Murakami

Makoto Miki

Toshiyuki Takauji

Seiji Kato

Mitsuo Kakuishi

Yutaka Awata

Hiroyuki Rokugawa

Masaaki Kawai

Atsushi Iwata

Akihiko Ito

Kazuhiro Kobayashi

Satoshi Ide

Seiji Miyoshi

Hisami Tanaka

Takashi Oka

Kazunari Tsubaki

Atsushi Manabe

The present invention provides an ophthalmic pharmaceutical composition containing acetylated hyaluronic acid and a pharmacologically acceptable carrier. Preferably, the average molecular weight of the acetylated hyaluronic acid is 10,000 to 1,000,000, and the acetyl group substitution number is from 2.0 to 4.0. In a preferred embodiment, this ophthalmic pharmaceutical composition is used in the treatment or prevention of dry eye, and in an even more preferred embodiment it is a dry-eye instillation.

Medicinal composition for ophthal use containing acetylated hyaluronic acid

Using a switching signal from a coarse/fine switching and operation mode switching circuit, the width of change of a counter control value during power up is increased, and the width of change is reduced once a steady state is reached. In the steady state, the frequency of updating is limited by a control signal from an update permit control circuit. In the steady state, the frequency band of a current source in an LD driving circuit is reduced in width.

Light output control circuit

Light output control device

A light output control circuit to update light output synchronously with input data in burst signal transmission system is disclosed. The circuit has a function of issuing light deterioration warning unerringly, which includes: a monitoring portion to detect light output emitted from a light emission element driven in accordance with transmission data; a level comparator to compare a monitoring signal outputted from the monitoring portion with a reference signal; a data detection portion to detect the existence of the transmission data; and an output controller to determine whether a light output deterioration warning is to be issued using an output signal of the data detection portion and an output signal of the level comparator.

Light output control circuit with a warning function of deteriorated light output

An optical transmitter circuit including a light receiving element, such as a photodiode, which monitors the optical output of a light emitting element such as a semiconductor laser. A current-voltage converting circuit supplies a drive current from a drive circuit to the light emitting element and converts the output voltage of the light receiving element into voltage. An APC amplifier compares the converted output signals and a reference signal, and a hold circuit holds the output signal of the APC amplifier and uses the output signal as a current control signal of the drive circuit. A &ldquo;1&rdquo; continuous signal detecting circuit detects the continuation of &ldquo;1&rdquo; in a specified number of bits in the input data (DATA) and updates the hold value in the hold circuit.

Optical transmitter circuit

In an amplifying circuit composed of a basic amplifier and a bias circuit thereof, a drive transistor drives a load transistor, and a reference current source biases a drive-side and a load-side supporting bias transistors with a constant current for generating a bias voltage of the load transistor. Also, a load resistor or a drive-side common-gate transistor is inserted between the drive transistor and the load transistor. Also, a load-side common-gate transistor is inserted between the load transistor and a power supply. In addition, the bulks and sources of the load transistor and the load-side supporting bias transistor are short-circuited.

Amplifier circuit having a particular biasing arrangement

A burst mode optical transmitter circuit comprises a semiconductor laser, a photodiode for monitoring the light output from the semiconductor laser, a current-voltage converting circuit for converting the current detected by the photodiode into a voltage, an APC amplifier, a holding circuit for holding, as a current control signal, the output signal from the APC amplifier, a driving circuit for supplying a driving current to the semiconductor laser according the current control signal from the holding circuit and the the data input in the burst mode, and a data interruption detecting circuit for detecting an interrupt period of the data input to the driving circuit to reset the holding circuit, in which the current control signal held in the hold circuit is reset by the reset signal, whereby a stable burst optical transmission can be performed stably with a simple construction.

Burst mode optical transmitter circuit

A drain terminal of a first N-channel MOS transistor is connected to an output side of a first current mirror input current via a voltage drop device, a first current mirror input current is supplied to the gate terminals of first, third, and fifth N-channel MOS transistors, and a second current mirror input current is supplied to the gate terminals of second and fourth N-channel MOS transistors.

High precision current output circuit

An interface circuit for interfacing between an integrated circuit (IC) on a transmitting side and an IC on a receiving side over a line on a printed circuit board comprises an output circuit implemented in the IC on the transmitting side and composed of a current source for supplying a given current and a switching circuit for cutting off the given current according to a binary signal and delivering the given current as a current signal to the line, and an input circuit implemented in the IC on the receiving side and composed of a transimpedance circuit whose input impedance is equal to the one of the line and which converts the current signal into a voltage signal, and a comparator for identifying the voltage signal relative to a given threshold voltage and reproducing the binary signal. This circuitry makes it possible to provide an interface circuit that can be implemented in a CMOS IC during CMOS processing and operated at a low voltage. A threshold voltage for use in identifying a signal on the receiving side is stabilized, thus realizing an interface circuit unsusceptible to influence of a change in CMOS processing or the like.

Interface circuit adaptive to high speed and low voltage operation

A digital adaptive equalizer equalizes received signals through digital filtering operations by changing filtering coefficients. It comprises a coefficient calculating unit for calculating the filtering coefficients by using one kind of parameters, such as distance, as an input to a function corresponding to the filtering coefficients and a filtering operation executing unit for executing digital filtering operations based on the filtering coefficients. A variable lag filter for adjusting the phase delay of received received signals is provided. A coefficient converting unit calculates a part or all of tap coefficients of the filter using at least one piece of timing control information.

Received data adjusting device

In a device for estimating a sampled value of an impulse response from input and output signals of a decision circuit which performs a signal decision procedure for reproducing a digital signal, there are provided a first part, operatively coupled to the decision circuit, for generating a first average of absolute values of samples of decided values obtained from the output signal of the decision circuit. A second part is also provided, operatively coupled to the decision circuit, for generating a second average of absolute values of samples of equalized outputs obtained from the input signal of the decision circuit. Also provided is a third part, operatively coupled to the first and second parts for generating a ratio of the first average and the second average, with the ratio being an estimate of the sampled value of the impulse response at a sampling point.

Device and method for estimating sampled value of impulse response and

An adjustable attenuator circuit in which sampled electric charges are partially transferred from a sampling capacitor to a charge dividing capacitor during a short time within each sampling period, and electric charges stored in the charge dividing capacitor are additively transferred to an integrating capacitor or are discharged to ground according to the content of a weighting coefficient which determines the attenuation factor of the adjustable attenuator circuit.

Adjustable attenuator circuit

An integrator for use in a switched capacitor-filter, in which switching elements are connected to an input and to an output of an operational amplifier included in the integrator for clamping the input and output to a ground potential during suspension of the integral operation, in order to prevent potentials at the input and output of the operational amplifier from varying and hence ensure rapid stabilization of the integral operation of the integrator.

Integrator for a switched capacitor-filter

A switched capacitor filter having at its input, a signal converter for creating so-called 100% sample and hold signals. The signal converter comprises a plurality of switched capacitors. The switched capacitors, connected in parallel with each other, receive the same successive input signals and supply the so-called 100% sample and hold input signals to the switched-capacitor filter. The switched capacitors, on one hand, charge each of said input signals sequentially and, on the other hand, alternately discharge the respective stored input signals one by one.

Switched-capacitor filter

A switched-capacitor filter provided with, at its input stage, a prefilter comprised only of a plurality of additional switched capacitors together with a switched capacitor common to the switched-capacitor filter. The switched capacitor common to the switched-capacitor filter is driven by primary clock pulses having a period T, while the additional switched capacitors are sequentially driven by secondary clock pulse groups. Each of the secondary clock pulse groups has the same period T, and the phases of the second clock pulse groups are shifted by T/2.sup.k, 2T/2.sup.k, 3T/2.sup.k . . . (2.sup.k -1)T/2.sup.k with respect to the first clock pulses (k is a positive integer). The sampled and held signals in the switched capacitors are supplied synchronously to the switched-capacitor filter.

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Kawasaki, Japan

Norio Ueno