Nippon Gakki Seizo Kabushiki Kaisha

Yamaha Corporation

Norio Tomisawa

Yasuji Uchiyama

Takatoshi Okumura

Toshio Takeda

Hideo Suzuki

Sadayuki Narusawa

Shinji Aoshima

Eiichiro Aoki

Minoru Ogita

Akio Imamura

Shingo Kamiya

Takehisa Amano

Mamoru Horino

Atsushi Takeuchi

Nobuyuki Tamori

A signal delay device comprises a CMOS gate circuit having an input terminal to which a binary input signal to be delayed is applied, an output terminal from which a delayed signal is derived and power voltage supply terminals to which operation power voltages are applied. The delay time of the CMOS gate circuit depends upon voltage applied to it and, utilizing this phenomenon, voltage control means is provided in a power supplying path for the CMOS gate circuit for controlling voltage applied to the CMOS gate circuit. The signal delay device using the CMOS gate circuit is applied to a combination of an FM modulator and FM demodulator to provide a delay circuit for an analog circuit.

Signal delay device

A signal delay device comprises a CMOS gate circuit having an input terminal to which a binary input signal to be delayed is applied, an output terminal from which a delayed signal is derived and power voltage supply terminals to which operation power voltages are applied. The delay time of the CMOS gate circuit depends upon voltage applied to it and, utilizing this phenomenon, voltage control means is provided in a power supplying path for the CMOS gate circuit for controlling voltage applied to the CMOS gate circuit, The signal delay device using the CMOS gate circuit is applied to various circuits including an analog signal delay circuit, a jitter absorption circuit and a fixed head type magnetic tape reproducing device.

Signal delay device using CMOS supply voltage control

A signal delay device comprises a CMOS gate circuit having an input terminal to which a binary input signal to be delayed is applied, an output terminal from which a delayed signal is derived and power voltage supply terminals to which operation power voltages are applied. The delay time of the CMOS gate circuit depends upon voltage applied to it and, utilizing this phenomenon, voltage control means is provided in a power supplying path for the CMOS gate circuit for controlling voltage applied to the CMOS gate circuit. The signal delay device using the CMOS gate circuit is applied to various circuits including a FM modulator or FM demodulator. The signal delay device will assure undistorted signals.

FM demodulation device and FM modulation device employing a CMOS signal

A signal delay device comprises a CMOS gate circuit having an input terminal to which a binary input signal to be delayed is applied, an output terminal from which a delayed signal is derived and power voltage supply terminals to which operation power voltages are applied. The delay time of the CMOS gate circuit depends upon voltage applied to it and, utilizing this phenomenon, voltage control means is provided in a power supplying path for the CMOS gate circuit for controlling voltage applied to the CMOS gate circuit. The signal delay device using the CMOS gate circuit is applied to various circuits including an analog signal delay circuit, a jitter absorption circuit and a fixed head type magnetic tape reproducing device.

Jitter control circuit having signal delay device using CMOS supply

A PWM circuit for generating a PWM wave which is pulse-width modulated in response to binary information and is used for a signal such as a motor driving signal in an R-DAT (rotary head type digital audio tape recorder) comprises a circuit for dividing binary information such as a motor speed error signal provided for generating a PWM wave into plural bit groups and generates PWM waves corresponding to numerical values of these plural bit groups, and a circuit for weighting the generated PWM waves in an analog manner at a ratio corresponding to orders of the respective bit groups and adding the weighted PWM waves. Since binary information is divided into plural bit groups, the bit number of each bit group is small so that the period of PWM wave can be shortened without reducing the quantization bit number of the binary information or shortening reference clock period whereby accuracy of an error signal can be improved when the invention is applied to, e.g., a motor drive device.

PWM circuit

A CMOS integrated circuit for signal delay comprises CMOS gate circuits connected in multiple stages which deliver out an input binary signal after delaying it by a predetermined delay time. The CMOS gate circuits are arranged in a folded pattern on an integrated circuit substrate and each row of the folded pattern including a part of the CMOS gate circuits in stages of an odd number. Each of the CMOS gate circuits consists of an N channel element and a P channel element cascade-connected to each other and gate patterns of the respective channels have their width and length adjusted in such a manner that value of operating currents in these elements become equal to each other when the same external voltage has been applied to these elements.

CMOS integrated circuit for signal delay

A disc rotation control device for a compact disc player comprises a stable rotation detection circuit for detecting whether rotation of a compact disc is in a stable state or in an unstable state, a phase control loop for phase-controlling the disc rotation and direct control means for directly controlling the disc rotation. The disc rotation is controlled by the phase control loop when the disc rotation is in a stable state and, if the disc rotation has become unstable, the control of the disc rotation is switched to one by the direct control means. During the phase control, even if an EFM signal reproduced from a disc has become unavailable for some reason, preceding phase difference data is held and used for the disc rotation control.

Disc rotation control device for a disc player

There is provided a data processing circuit for processing symbol data read from a disc of a digital audio system such as a DAD player. Each of the symbol data read from the disc is first stored into a buffer register and then transferred therefrom to a symbol memory in accordance with internal pulse signals, and the number of the pulse signals generated during a period required to process one frame of symbol data is greater than that of symbol data contained in one frame of symbol data. An address data for addressing a desired area of the symbol memory is formed by adding a reference address data generated by counting the internal frame synchronization signals to a relative address data generated by adding together a specific pair of addressing data read out from an address memory, the address memory storing a plurality of groups of addressing data to be used in accordance with each mode of operation of this circuit. When the symbol data is written into the symbol memory, the reference address data is modified by adding an output of an up/down-counter to compensate for jitters of the symbol data, the up/down-counter counting frame synchronization signals discriminated from the data read from the disc in one of upward and downward directions and counting the internal frame synchronization signals in the other of upward and downward directions.

Data processing circuit for digital audio system

In picking up recorded data from a revolving optical disc by an optical reproduction system in an optical type disc reproduction device and detecting time data of Q subcode from the picked up data for performing operations such as searching a target position, the position control device according to this invention facilitates handling of data in cases such as computing time difference by converting detected present time data from a BCD code into a binary code by a BCD/binary conversion circuit and using the binary coded data. For searching a target position, time difference is detected by a time difference detection circuit on the basis of a difference between the binary coded present time data and target time data and a relative position of the optical reproduction system with respect to the optical disc is changed by a relative position change driver such that the time difference is reduced to zero.

Position control device for an optical reproduction system in an optical

A subcode signal reading circuit in a compact disc player of the compact disc digital audio system comprises an EFM demodulation circuit which receives an EFM reproduction signal reproduced from a disc, EFM-demodulates the EFM reproduction signal and outputs a demodulated eight-bit signal, a first register in which a Q subcode included in the demodulated eight-bit signal provided by the EFM demodulation circuit is written in eight-bit fashion, a second register to which contents of the first register are transmitted and an error detection circuit for detecting whether or not the Q subcode produced by the EFM demodulation circuit contains error. Transmission of the contents of the first register to the second register is controlled by an output of the error detection circuit in such a manner that the transmission is made when no error has been detected by the error detection circuit. An output of the second register is used in the disc player as a correct Q subcode to be read.

Subcode signal reading circuit in an optical type disc player

In a digital system, there is provided a circuit for detecting and correcting errors in a group of data using Reed-Solomon codes. The group of data is first stored in a memory, and syndromes of the data are produced by a syndrome calculation circuit and fed to an internal data bus. A first data conversion circuit converts the syndromes on the internal data bus into logarithmic values and a multiplier-divider circuit executes multiplication or division of the data on the internal data bus by addition and subtraction operations of the logarithmic values. A second data conversion circuit converts antilogarithmically data from the multiplier-divider circuit, and an addition and subtraction circuit executes addition or subtraction of the data from the second data conversion circuit. An error detection circuit detects whether a single error exists in the group of data in accordance with the syndromes, and an error detection signal representing existence of error and an error location signal representing error location are produced. An address control circuit addresses the memory in accordance with the error detection signal and the error location signal so that the memory outputs an error data. A data correction circuit adds one of the syndromes representing amount of data error on the internal data bus to the error data outputted from the memory to produce its correct data. A double data error can be detected and corrected using Reed-Solomon codes in a similar manner.

Data error detection and correction circuit

There is provided a counter circuit operable in synchronism with a frame of a digital data signal of a digital audio system even if a frame synchronization signal is not detected. The counter circuit comprises a detection circuit for detecting the frame synchronization signal of the digital data signal to produce a frame synchronization detection signal. A series of counters repeatedly count clock pulses reproduced from the digital data signal to produce a count signal when the count of the series of counters reaches a value corresponding to the number of channel bits includes in one (1) frame of the digital data signal. A reproduction frame sychronization signal is generated in response to the frame synchronization signal when the count of the series of counters is within a predetermined range, the reproduction frame synchronization signal resetting the counters. The reproduction frame synchronization signal is also generated in response to the count signal when the count of the series of counters is within the predetermined range and when the frame synchronization detection signal is not outputted from the frame synchronization signal detection circuit, the reproduction frame synchronization signal resetting the counters.

Counter circuit operable in synchronism with frame or digital data signal

A simplified clock-signal reproducing circuit for reproducing a clock signal from a repetitive pulse signal or a digital signal such as an EFM signal read from a compact disc as a data recording medium of the compact disc digital audio system is provided. A voltage-controlled oscillator generates a first repetition signal, and a second repetition signal is formed from the first repetition signal, the second repetition signal being the clock signal. The repetitive pulse signal is latched by a first latch in response to the clock signal, and a signal which is a delayed output of the first latch is latched by a second latch in response to the clock signal. A voltage representing a phase difference between a clock signal in the repetitive pulse signal and the clock signal generated by the voltage-controlled oscillator is generated in accordance with a first phase difference between the input and output signals of the first latch and a second phase difference between input and output signals of the second latch. This voltage is applied to the voltage-controlled oscillator to thereby control the frequency of the first repetition signal so that the first and second phase differences become equal to each other and that the clock signal generated by the voltage-controlled oscillator and the clock signal existing in the repetitive pulse signal coincide in phase with each other.

Clock-signal reproducing circuit including voltage controlled oscillator

A digital signal processing device is disclosed. At an intermediate time point between respective sample data of a digital signal input is interpolated data expressed by the formula ##EQU1## wherein R.sub.l, m and n are positive integers. The digital signal interpolated with this interpolation data d is applied to a digital-to-analog converter where it is converted to an analog signal. This interpolation serves as a low-pass filter for removing unnecessary harmonic components, with the result that a analog filter used in a posterior stage after the digital-to-analog converter requires no steep characteristics and hence can be of a remarkedly simple structure and be manufactured at reduced cost.

Digital signal processing device

Analog output signals of a key touch sensor and tonal effect setting manual operators are respectively time division multiplexed and thereafter are converted to digital signals by using an analog to digital converter on a time shared basis. The key touch sensor capable of detecting a key touch of a depressed key can also be used for obtaining an initial touch detection signal by additionally providing a device for holding a peak value of an output signal of the sensor at the beginning of depression of the key. Control factors of various tonal effects are controlled in response to these converted digital signals. Control factors of an attack pitch control effect are controlled in response to the key touch. In imparting a delay vibrato effect, the attack pitch control is automatically applied before the delay vibrato is initiated. In imparting a vibrato effect, the attack pitch control is automatically applied and the vibrato is applied thereafter if a key has been depressed in a staccato form. Selection as to whether a slur effect should be imparted or not is automatically made depending upon whether the key has been depressed in a legato form or not. A modulating signal for the vibrato is obtained by repeatedly calculating a numerical value setting the frequency of the modulating signal by a first calculator and repeatedly calculating a small value setting the amplitude of the modulating signal by a second calculator in response to a carryout signal of the first calculator.

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Hamamatsu, Japan

Norio Tomisawa