Kabushiki Kaisha Toshiba

Norio Ootani

Hiroaki Hazama

Seiichi Mori

Kazuhito Narita

Hirohisa Iizuka

A nonvolatile semiconductor memory device is provided having a plurality of electrically rewritable nonvolatile memory cells connected in series together. A select gate transistor is connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gate transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with a different bias voltage as that for the other memory cells.

NAND type memory with dummy cells adjacent to select transistors being biased at different voltage during data erase

A nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit comprises a semiconductor substrate, isolation insulating films for defining a plurality of element formation regions, each of the isolation insulating films being buried in an isolation trench provided in the semiconductor substrate, a floating gate provided in each of the element formation regions via a first gate insulating film, a control gate provided on the floating gate via a second gate insulating film, and source and drain regions provided in the semiconductor substrate in self-alignment with the control gate, wherein the floating gate is self-aligned at an isolation end in a direction of a channel width, and comprises a plurality of polysilicon films.

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Yokkaishi, Japan

Norio Ootani