Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Norio Masui

Yukihiko Shimazu

Akira Oizumi

Shigeo Mizugaki

Akira Mukai

Provided is a TLB that can translate rapidly a virtual address to a physical address at small power consumption. A tag entry part () includes an ASID hold part (), virtual address hold part (), valid bit part (), ASID comparison judgment part (), and a virtual address comparison judgment part (). By an ASID match line (), a plurality of CAM cells () of the ASID hold part () are connected in parallel to each other and also connected to the ASID comparison judgment part (). By a virtual address match line (), a plurality of CAM cells () of the virtual address hold part () are connected in parallel to each other and also connected to the virtual address comparison judgment part (). An ASID effective signal () is provided from the ASID comparison judgment part () to the virtual address comparison judgment part ().

Address translation unit performing address translation from virtual address to physical address

A bus control circuit includes cycle registers provided with areas for holding signal levels of system-to-external bus control signals such that each of the cycle registers is provided for a corresponding cycle. A default register, additionally included in the bus control circuit, holds signal levels of the system-to-external bus control signals in a normal state. The signal levels of the system-to-external bus control signals held in the corresponding areas in the cycle registers are output cycle by cycle. When the normal state takes over, the signal levels held in the corresponding areas in the default register are output.

Bus control circuit effecting timing control using cycle registers for respective cycles holding signal levels corresponding to bus control signals that are output by arrangement of signal level

A central processing unit (CPU) (162) furnishes an interrupt request acknowledge signal (107) to an interrupt control unit (ICU) (101) in response to an interrupt request signal (106) from the ICU (101). Then the CPU (102) reads the address specifying the origin of a program to process the interrupt request. After that, the CPU (102) causes the interrupt request acknowledge signal (107) to make a transition to its deactivated state. In response to the transition in the interrupt request acknowledge signal, the ICU (101) causes the interrupt request signal (106) to make a transition to its deactivated state and then clears an interrupt priority level signal (108) showing the priority level of the interrupt request (106).

Method of processing interrupt requests and information processing

A microprocessor accesses a first and second area of an external memory by outputting common addresses excluding a least significant bit of the actual addresses. The first area stores even addresses and the second area stores odd addresses. The microprocessor comprises a microprocessor core generating the actual addresses, an address counter generating a pre-output address value obtained by, at a start of every accessing to the second area, sequentially incrementing from an initial value obtained by excluding the least significant bit from the actual address generated by the microprocessing core, an address latch latching the pre-output address value, a control circuit controlling the address latch to latch the pre-output address value and provide the pre-output address value to the memory after accessing the memory, and an address comparator. The address comparator, at the time of accessing the first and second areas, compares the value obtained by excluding the least significant bit from the actual address generated by the microprocessing core and the pre-output address value latched by the address latch, and outputs a hit signal upon coincidence. The control circuit controls the address counter and the address latch to latch the value obtained by excluding the least significant bit from the actual address when the address comparator does not output a hit signal. Thus, an access time can be shortened at reading a plurality of sequential data successively from the memory whose access time is relatively long.

Microprocessor having address pre-outputting function and data processor

A semiconductor apparatus for data processing capable of reading a control code to the outside by adding only a small quantity of logical circuit and wiring area, by being provided with an incrementer 305 for incrementing the output of a .mu.-address register 302, a counter 102 for counting the number of overflows of the incrementer 305, a second selector 103 for dividing and selecting the control code outputted from a .mu.-ROM 301 responsive to a count value of the counter 102, and with a third selector 104 for selecting the output of the second selector 103 at the time of control code reading mode and for inputting it to the operand address register 309.

Apparatus for sequentially reading microcode words wider than an

A microcomputer provided with improved interrupt handling. The frequency of a clock signal supplied to the central processing unit is increased to shorten the interrupt holding time when relatively many interrupts are occurring. When few interrupts are occurring, the frequency of the clock signal is decreased thereby reducing power consumption. The invention includes a holding factors register for storing the number of interrupt factors being held by an interrupt controller and an interrupt nesting counter for storing the number of nested interrupts in the central processing unit. The numbers stored in the holding factors register and interrupt nesting counter are compared to preset numbers. A clock control circuit changes the frequency of the system clock signal in accordance with the comparison result thereby changing the frequency of the clock signal depending on the number of occurrences of interrupts.

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Tokyo, Japan

Norio Masui