Seiko Epson Corporation

Seiko Epson Corporaiton

Seiko Epson Cpropration

Norio Koizumi

Shigeki Aoki

Yoichi Imamura

Masahiko Tsuchiya

Yohichi Imamura

Tsuyoshi Tamura

The invention provides display controllers, display units and electronic apparatuses using the same, which can achieve transfer rates that can accommodate increases in the amount of display data that may result from increases in the screen size of liquid crystal panels in the future with low power consumption. The display unit includes a liquid crystal panel (display section), a display data RAM that stores display data for at least one frame, an X driver IC (display controller) that display-drives the liquid crystal panel at a given frame cycle, and a Y driver IC that scan-drives the liquid crystal panel. Display data is supplied from the MPU to the X driver IC through a differential IF. The MPU supplies display data at a high-speed transfer rate with the differential IF, using a dummy blanking period, and stops the operation of the differential IF until the next display data transfer timing.

Display controller, display unit and electronic apparatus

A display driver capable of implementing natural moving image display with a reduced power consumption, based on display data of following frame is generated on a cycle longer than a read cycle for display data from a built-in RAM, and a display unit and an electronic instrument having the display driver. A display driver IC with a built-in RAM stores in an FIFO memory compressed data input on a cycle longer than a drive cycle that is based on the display data, uses an MPEG decoder circuit to decompress the compressed data on a cycle substantially equivalent to the read cycle of the display data RAM to generate the display data, and writes the display data into the display data RAM prior to the read operation at a speed equal to or higher than the reading speed.

Display driver, and display unit and electronic instrument using the same

The semiconductor device according to the present invention comprises at least one first semiconductor circuit in which first currents (Ih&ngr;a to Ih&ngr;a ) excited by external light (h&ngr;) are produced. It further comprises at least one second semiconductor circuit ( ) which is electrically connected to the first semiconductor circuit ( ) and in which second currents (Ih&ngr;b to Ih&ngr;b ) excited based on the external light (h&ngr;) and canceling a part or all of the voltage fluctuation produced by the current increment of the first currents (Ih&ngr;a to Ih&ngr;a ) when the external light (h&ngr;) shines are produced.

Semiconductor device, liquid crystal display, and electronic equipment including the same

A semiconductor device capable of preventing malfunctions of instantaneous lighting, and comprises a drive circuit, a drive control circuit, and a power supply circuit. The power supply circuit has a boosting circuit which is provided with a first power supply potential VDD being a ground potential from an external power supply and a second power supply potential VSS, being a potential other than the ground potential, and raises the absolute value of the second power supply potential VSS and charges to the capacitor; and a bias generating circuit generating a potential to be supplied to the drive circuit and drive control circuit based on the output potential of the boosting circuit. A first power supply potential VDD and the potential of the bias generating circuits are supplied to the drive circuit which outputs a potential selected from the potentials V to V supplied in accordance with the control of the drive control circuit during a normal power supply period, and, during a power supply emergency, in which the absolute value between the first and the second potentials VDD and VSS becomes lower than a prescribed vale, tuns on a P-type MOS transistor based on a LOW active signal from a buffer, whereby all potentials output from the drive circuit are forcibly set to the first power supply potential VDD.

Semiconductor device, and liquid crystal device and electronic equipment using the same

A semiconductor device that is capable of preventing erroneous operation such as momentary lighting, comprising a booster circuit to which first and second power supply potentials VDD and VSS are supplied from an external power source, for boosting the absolute value of the potential difference therebetween and charging the boosted potential to a capacitor. This booster circuit has a plurality of transistors and a plurality of capacitors, and the boosted potential is charged to one of the plurality of capacitors in accordance with how the plurality of transistors are turned on or off. The gates of a plurality of transistors are connected to output lines of first and second NAND circuits, to which the output of a comparator is input through a buffer. The output of the comparator is at a low level when the second power supply potential VSS is higher than a reference potential VREG, such as when the power is forcibly cut, in which case the charge in one of the plurality of capacitors is discharged, based on the outputs from the first and second NAND circuits.

Electrical device with booster circuit

A semiconductor device capable of preventing malfunctions of instantaneous lighting, and comprises a drive circuit, a drive control circuit, and a power supply circuit. The power supply circuit has a boosting circuit which is provided with a first power supply potential VDD being a ground potential from an external power supply and a second power supply potential VSS, being a potential other than the ground potential, and raises the absolute value of the second power supply potential VSS and charges to the capacitor; and a bias generating circuit generating a potential to be supplied to the drive circuit and drive control circuit based on the output potential of the boosting circuit. A first power supply potential VDD and the potential of the bias generating circuits are supplied to the drive circuit which outputs a potential selected from the potentials V0 to V5 supplied in accordance with the control of the drive control circuit during a normal power supply period, and, during a power supply emergency, in which the absolute value between the first and the second potentials VDD and VSS becomes lower than a prescribed vale, tuns on a P-type MOS transistor based on a LOW active signal from a buffer, whereby all potentials output from the drive circuit are forcibly set to the first power supply potential VDD.

A semiconductor device that is capable of preventing erroneous operation such as momentary lighting, having a booster circuit to which first and second power supply potentials VDD and VSS are supplied from an external power source, for boosting the absolute value of the potential difference therebetween and charging the boosted potential to a capacitor. This booster circuit has a plurality of transistors and a plurality of capacitors, and the boosted potential is charged to one of the plurality of capacitors in accordance with how the plurality of transistors are turned on or off. The gates of a plurality of transistors are connected to output lines of first and second NAND circuits, to which the output of a comparator is input through a buffer. The output of the comparator is at a low level when the second power supply potential VSS is higher than a reference potential VREG, such as when the power is forcibly cut, in which case the charge in one of the plurality of capacitors is discharged, based on the outputs from the first and second NAND circuits.

Semiconductor device with internal power supply circuit, together with liquid crystal device and electronic equipment using the same

An oscillation device includes a buffer device, a feedback device for feeding back an output of the buffer device to an input thereof and a charging device and a discharging device connected to the input of the buffer device. The charging device includes a first switching device that is turned on and off based on the output of the buffer device and a first current control device that controls the current flowing into the input of the buffer device through the first switching device. The discharging device includes a second switching device that is turned on or off based on the output of the buffer device and a second current control device that controls the current flowing out of the input of the buffer device through the second switching device. The first and second switching devices include first and second transistors and the first and second current sources that include third and fourth transistors. The oscillation device includes a bias circuit that controls at least the current ratio of the first and second current of the first and second current sources by controlling bias voltages applied to first and second bias terminals of the oscillation device.

Oscillators with charging and discharging circuits

The present invention provides a matrix type display device which simplifies the process in a display signal generating circuit while relieving the load on an external CPU, and which arranges freely character and icon display areas while preventing the quality of display from being degraded by the shadow phenomenon and others. A display code memory stores character display codes and icon display codes for one image at a desired address arrangement. A pattern generating circuit transfers image patterns for the display codes to a display signal transferring circuit through a multiplexer. A decoder selecting device is responsive to a decoder select signal to select a decoder, thereby controlling voluntarily the timing of latch signal generation. Display signal input in the time division manner is latched in first and second latch circuits through the latch signal. Thereafter, the display signal is transferred to a signal electrode driving circuit through a line memory to display an image on a matrix panel.

Matrix type display device, electronic system including the same and

An oscillation device and a display data processing device adjust variables such as the duty ratio of the oscillation frequency, and control autonomously timings between components such as memories. First and second switching devices disposed within charging and discharging devices are turned on and off by an output of a MOS buffer, enabling adjustment of the frequency and duty ratio of an oscillation signal. Equivalent circuits are provided corresponding to display data RAM, CGROM, and address decoders, data is read sequentially from the display data RAM and the CGROM when an EIRAM signal is enabled, and a DLAT signal is stored in a driver circuit. The equivalent circuits enable each of EIROM, EILAT, and RS signals at points when the read data is confirmed or thereafter. When the RS signal is enabled, EIRAM and other signals are sequentially disabled and the display data RAM and other components switch to a precharge operation.

Oscillation device, display data processing device, matrix-type display

The present invention provides a matrix type display device which simplifies the process in a display signal generating circuit while relieving the load on an external CPU, which arranges freely character and icon display areas while preventing the quality of display from being degraded by the shadow phenomenon and others. A display code memory stores character display codes and icon display codes for one image at a desired address arrangement. A pattern generating circuit transfers image patterns for the display codes to a display signal transferring circuit through a multiplexer. A decoder selecting device is responsive to a decoder select signal to select a decoder, thereby controlling voluntarily the timing of latch signal generation. Display signal input in the time division manner is latched in first and second latch circuits through the latch signal. Thereafter, the display signal is transferred to a signal electrode driving circuit through a line memory to display an image on a matrix panel.

Growing community of inventors

Suwa, Japan

Norio Koizumi