Hitachi, Ltd.

Norio Hirako

Atsushi Tanaka

Akiyoshi Hashimoto

Shoji Kato

In a storage system directly connected to a network, if conventional interfaces and protocols are used when an I/O command issued from a file server is transmitted to the storage system, the command/data is serially transferred via a single transfer path so that the performance is lowered. Conventional interfaces do not provide the means to notify the storage system of the failure at the file server. The file server and a channel adapter of the storage system are mounted on the same board and connection paths therebetween are controlled so that a plurality of protocols can be operated independently. A path independent from a command/data path is provided between the file server and channel adapter, and the received failure information is stored in a shared memory of the storage system and used for the fail-over.

SAN/NAS integrated storage system

In a data input/output with other apparatus, a data transfer controller (DTC) of a storage controller multiprocesses a data transfer with the other apparatus by utilizing a saving/recovering operation and suppresses a load therefrom, thereby improving performance thereof. A first storage apparatus includes two DMA units in a data transfer LSI of the DTC, uses them to process one or more data transfers concurrently, uses the saving or recovering operation to a memory #also in one DMA unit to process the data transfer while the data transfers are switched, thereby multiprocessing a plurality of data transfers. Based on an instruction from the IOC, the DTC makes one of the DMA units recover the necessary data transfer information and data from the memory #and transfer the data to the memory, and concurrently the other of the DMA units, which is not processed presently, save in advance, to the memory #, the data transfer information and the data stored in the memory.

Storage apparatus

A storage device controller includes a channel controller to receive a data input/output request sent from an information processor, a disk controller, and a cache memory. The channel controller includes a communication interface unit for the information processor, a data transfer unit connected via a first bus to the communication interface unit, and a processor connected via a second bus to the data transfer unit. The communication interface unit sends a read command to the data transfer unit for the processor. When the first bus conforms to a first communication protocol, the data transfer unit sends a split response to the communication interface unit. The data transfer unit sends the read command to the processor. The processor sends the split response and readout data corresponding to the read command to the data transfer unit. The data transfer unit receives and sends the readout data to the communication interface unit.

Growing community of inventors

Hadano, Japan

Norio Hirako