Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Norio Higashisaka

Akira Ohta

Tetsuya Heima

Masaaki Shimada

Shinsuke Watanabe

Tsutomu Yoshimura

Kenichi Horiguchi

Yoichi Nogami

Toshiaki Kitano

Jun Takaso

Jun Takasou

A field effect transistor includes: a semiconductor substrate having a main surface; a plurality of source electrodes and a plurality of drain electrodes alternately disposed and ohmic-connected with the main surface of the semiconductor substrate; a plurality of gate electrodes Schottky-connected with the main surface of the semiconductor substrate and respectively disposed between the plurality of source electrodes and the plurality of drain electrodes; and a Schottky electrode Schottky-connected with the main surface of the semiconductor substrate, wherein each of the plurality of drain electrodes has first and second portions separated from each other, a sum of widths of the first and second portions of each drain electrode is smaller than a width of one source electrode, the Schottky electrode is disposed between the first portion and the second portion of the drain electrode.

Field effect transistor

A laser diode drive circuit includes a first transistor having a collector connected to an anode of a laser diode; a second transistor having a collector connected to a cathode of the laser diode; a constant current circuit connected between a ground point and emitters of the first and second transistors; a first high-pass filter connected between the base and the collector of the first transistor; and a second high-pass filter connected between the base and the collector of the second transistor.

Laser diode drive circuit

An amplifier circuit includes a first differential amplifier circuit, a second differential amplifier circuit which amplifies an output signal from the first differential amplifier circuit, and an active feedback circuit which performs waveform shaping on the output signal from the first differential amplifier circuit by feeding back an output signal from the second differential amplifier circuit. The active feedback circuit includes first and second transistors having collectors or drains respectively connected to respective output nodes of the first differential amplifier circuit, bases or gates respectively connected to two output nodes of the second differential amplifier circuit, and emitters or sources connected in common, and a first current source which has a first end connected to the emitters or sources of the first and second transistors, and a second end connected to a low-voltage power supply, and producing a current that can be externally adjusted.

Amplifier circuit

A variable delay circuit that delays an input signal for a desired time and outputs the delayed signal includes N (N is an integer of 2 or more) load transistors and N control transistors for controlling the load transistors respectively connected in pairs in series to form N load transistor pairs. The load transistor pairs are connected in parallel to form a load transistor group. A switching transistor that is turned on or off according to an input signal input to a gate, and the load transistor group are connected in series between first and second power supplies. The input signal is delayed according to control signals that are respectively input to the control transistors, and a delayed signal is output from a connection node of the load transistor group and the switching transistor. Since no selector is required, a delay circuit operation due to differences in delay times between paths in a selector is avoided, thereby obtaining a variable delay circuit having minute resolution and a good yield.

Variable delay circuit

A semiconductor device includes an input terminal and an output terminal; a delay circuit including N (N=integer) unit delay circuits connected in series between the input terminal and the output terminal, earn unit delay circuit including first and second two-input NOR or NAND circuits connected in series, the second two-input NOR or NAND circuit being nearer to the output terminal than the first two-input NOR or NAND circuit, a first input of each first two-input NOR or NAND circuit being connected to the input terminal, and an output of each first two-input NOR or NAND circuit being connected to a first input of the second two-input NOR or NAND circuit of each unit delay circuit; and a control circuit outputting individual control signals, each control signal being applied to a respective second input of the second two-input NOR or NAND circuit included in each unit delay circuit, wherein delay time in signal transmission from the input terminal to the output terminal varies in response to the control signals. The number of elements per unit resolution is reduced, and variations in the delay time are reduced by the reduced element number so the linearity of the delay circuit is improved. Further, the layout is simplified as compared with the conventional delay circuit.

Semiconductor device

A variable delay circuit including an input terminal to which a signal to be delayed is input, a delay gate connected to the input terminal, a logical gate to which an input to the delay gate and an output from the delay gate are input and which forms a delayed signal, and an output terminal outputting the delayed signal formed by the logical gate. A control signal for controlling the delay gate is input to the delay gate.

Variable delay circuit and a variable pulse width circuit

A multiplexer includes an n-th stage as a final output stage (n=integer, 2.ltoreq.n); j stages (j=integer, 1.ltoreq.j.ltoreq.n-1), the n-th stage including a D flip-flop having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the D flip-flop synchronizing the clock signal with the serial data; and a j-th stage including m.sup.n-j-1 (m=integer, 2.ltoreq.m) multiplexer blocks, each multiplexer block including D flip-flops and having data input terminals for receiving m parallel data inputs and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, and converting the parallel data into serial data in response to the second clock signal. The multiplexer further includes a variable delay circuit connected to the data input terminal of each multiplexer block in one of the second to the n-th stages for delaying the data input by a variable delay time. Therefore, even when the delay times of the constituents of the circuit vary due to device parameters or temperature, the timing of the data input can be adjusted by the variable delay circuit.

Multiplexer and demultiplexer

In a variable delay circuit including a high-speed clock generator receiving a trigger signal and outputting a pulse signal after a desired time interval upon rising of the trigger signal and a coarse delay signal generator, the high-speed clock generator includes a rising edge detector receiving the trigger signal, detecting a rising edge of the trigger signal, and outputting an edge detecting pulse having a time interval, and an asynchronous reset oscillator receiving the edge detecting pulse, being reset upon rising of the edge detecting pulse, and generating a high-speed clock upon falling of the edge detecting pulse. The high-speed clock generator of the variable delay circuit is realized without using analog circuits. Further, since the high-speed clock generator includes no PLL, it is not necessary to provide analog circuits, such as charge pump and VCO, in a digital LSI and, therefore, special considerations for the analog circuits are eliminated.

A variable delay circuit includes a gate chain of first to n-th delay gates (n is an integer larger than 2) connected in series to each other via delay gate wirings having respective wiring lengths, the first delay gate receiving an input signal for delay; first to n-th separator gates to which the outputs of the first to n-th delay gates are input, respectively; first to n-th separator gate wirings having wiring lengths successively shortened from the first to n-th separator gate, first ends respectively connected to the first to n-th separator gates, and second ends connected to an n:1 selector, for selecting one of the outputs of the first to n-th separator gates in according with a select signal, and a select signal generating circuit for controlling the n:1 selector. The variable delay circuit has no loss of resolution due to parasitic capacitance of the delay gate wirings.

A logic gate circuit includes a resistor, a current limiting circuit, a switching transistor, and a load transistor, the source of load transistor being connected to the drain of the switching transistor, the gate of the switching transistor being connected to an input terminal, the resistor being connected between the source of and the gate of the load transistor, and the current limiting circuit being connected between the gate of the load transistor and the source of the switching transistor. By using this logic gate circuit in the low speed operating section of an LSI, the dissipation current and the chip area of the LSI can be reduced even when the gate width and the threshold voltage of the load FET are the same as those in the high speed operating section.

Logic gate circuit and digital integrated circuit

A shift register circuit includes a first two-input NOR circuit to which a first data signal and a selection signal are input, a second two-input NOR circuit to which a first reverse data signal having an opposite phase from the first data signal and the selection signal are input, a third two-input NOR circuit to which a second data signal and a reverse selection signal having an opposite phase from the selection signal are input, a fourth two-input NOR circuit to which a second reverse data signal having an opposite phase from the second data signal and the reverse selection signal are input, a first three-input NOR circuit to which output signals from the first and third two-input NOR circuits and the clock signal are input, and a second three-input NOR circuit to which output signals from the second and fourth two-input NOR circuits and the clock signal are input. Since the three-input NOR circuits are employed, the number of NOR circuits through which the input data signal travels is decreased, resulting in an increase in the operation speed of the shift register circuit.

Shift register circuit with three-input nor gates in selector circuit

Disclosed is a logic circuit performing a quasi-complementary operation. This logic circuit includes a load transistor having a drain connected to a first power supply, a drive transistor having a source connected to a second power supply, a level shift diode connected between a source of the load transistor and a drain of the drive transistor, a resistor connected between a gate of the load transistor and the first power supply, an input portion for applying a signal for complementarily turning on the load transistor and drive transistor in response to an input signal, and a resistor connected between a gate of the drive transistor and the second power supply. Therefore, a gate potential of the load transistor is set to a potential which is always higher than a drain voltage, so as to prevent an output high level from being lowered and expand a logic voltage swing. Further, there is disclosed a logic circuit in which a plurality of quasi-complementary logic circuits are coupled by a wired logic. This circuit configuration enables the number of gate stages to be reduced in case where the plurality of logic circuits are coupled.

Quasicomplementary MESFET logic circuit with increased noise imunity

In an NOR logic circuit employing an MES (Metal Semiconductor Junction) field effect transistors, an MES field effect transistor 2 for driving an output stage operates in response to an input signal applied to an input terminal 101 or 102 to output an output signal from an output terminal 200. In this operation, an MES field effect transistor 4 for pull-down of input operates in response to an output signal fed back by a feedback circuit comprising a diode 5 and a current power supply transistor 3 to charge and discharge the gate of the transistor 2. Therefore, the transistor 2 can operate promptly and, as a result, the logic circuit can be operated at a high operating speed.

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Tokyo, Japan

Norio Higashisaka