Kabushiki Kaisha Toshiba

Norio Hagiwara

Minoru Nagata

Kenichi Hirashiki

Tsutomu Nakashima

Kazuhisa Sakihama

In one embodiment, a current mirror circuit includes first to fourth insulated gate field effect transistors (FETs), and a bias circuit. The gate electrodes of the first and second FETs are connected to each other. The source electrode of the third FET is connected to the drain electrode of the first FET, and the drain electrode of the third FET is connected to the gate electrodes of the first and second FETs and a current input terminal. The gate electrode of the fourth FET is connected to the gate electrode of the third FET, the source electrode of the fourth FET is connected to the drain electrode of the second FET, and the drain electrode of the fourth FET becomes a current output terminal. The bias circuit is configured to provide a bias voltage to the gate electrodes of the third and fourth FETs.

Current mirror circuit

A semiconductor memory device having information data storing cells and error correction data storing memory cells. When information data is inputted, error correction data related to the information data is formed. In a usual use, the information data and the error correction data are stored in the corresponding memory cells. An external test signal, inputted as the information data, can be stored in the error correction data storing memory cells by a write control signal. In a usual use, the information data stored in the information data storing cells are outputted, as they are or corrected if erroneous. The test signal stored in the error correction data storing memory can be outputted by an output control signal.

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Tokyo, Japan

Norio Hagiwara