Nec Corporation

Norio Funahashi

Hirofumi Saito

Toshihide Tsuboi

Yuji Okamoto

A frequency detection circuit has a transistor switching device between first and second electric potentials, and a gate applied with a clock signal. A resistor and a capacitor are connected in parallel between the output of the transistor switching device and the second potential. The capacitor is charged toward the first potential when the clock signal assumes one level and discharged toward the second potential in accordance with a time constant determined by the resistor and the capacitor when the clock signal changes to the other level. A comparison device connected to the output of the transistor switching device compares an output voltage of the transistor switching device with a predetermined threshold voltage and delivers an AC signal when the clock signal is small causing the output voltage of the transistor switching device to cross the threshold voltage during discharge of the capacitor, but a DC signal when the frequency of the clock signal is large causing the output voltage of the transistor switching device not to cross the threshold voltage.

Frequency detection circuit

A semiconductor device includes first and second elements, a light-shielding member, and a comparator. The first and second elements are formed on the same substrate, change in electrical characteristics upon irradiation of ultraviolet rays, and hold the changed states. The first element has the same arrangement as that of the second element. The light-shielding member is formed on the first element to shield ultraviolet rays. The comparator compares the electrical characteristics of the first and second elements and outputs an abnormality detection signal on the basis of the comparison results.

Semiconductor device

An EEPROM device comprises a memory cell array having a plurality of non-volatile memory cells respectively disposed at locations defined by word lines and bit lines and memorizing pieces of data information in a rewriteable manner, respectively, a row address decoder circuit responsive to an address signal indicative of a row address for selectively activating one of the word lines, a column address decoder circuit responsive to an address signal indicative of a column address for selecting one of the bit lines, and a data control unit selectively carrying out erasing, write-in and read-out operations on one of the non-volatile memory cells, in which the row address decoder circuit is further operative to concurrently activate every second word line in the presence of the row address signal indicative of a first state and to concurrently activate the other word lines in the presence of the row address signal indicative of a second state in a testing mode of operation, and in which the data control unit carries out the erase and write-in operations on a plurality of the non-volatile memory cells coupled to the word lines to be activated in the testing mode of operation.

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Kanagawa, Japan

Norio Funahashi