International Business Machines Corporation

Norio Fujita

Masahiro Murakami

Junka Okazawa

Masahiro Hori

David Alan Burton

Robert Louis Morton

Koji Nakase

Toshio Sunaga

Hiroaki Kubo

Satoshi Yamazaki

Yoshifumi Sakamoto

Tetsu Kubota

Mashahiro Murakami

A computer system including a CPU and a memory subsystem connected via a system bus to communicate with each other, wherein the memory subsystem comprises a memory controller connected to the system bus, the computer system includes an up/down counter for counting a number of access requests and a number of requests other than access requests, a comparator for comparing the count of the up/down counter with a predetermined threshold value stored in a register, and a clock gate circuit for generating clock gate signals to decimate an operating clock of the memory controller in response to the comparison result of the comparator.

Memory subsystem and computer system

A method including estimating an access request frequency from a CPU to a memory subsystem by counting a number of CPU access requests and a number of requests other than CPU access requests, wherein the CPU is connected to the memory subsystem via a system bus, and the memory subsystem includes a memory controller connected to the system bus, and a DDR memory, including the estimated access request frequency with a predetermined threshold value stored in a register, generating a clock gate signal to decimate an operating clock of the memory controller in response to a result of comparing the estimated access request frequency with the predetermined threshold value, generating a dummy cycle signal to delay the timing of signal data output from the memory controller to the system bus, and generating a clock enable signal to decimate an operating clock of the DDR memory.

An apparatus configured to write, in a non-volatile memory, an address conversion table for wear leveling of the non-volatile memory includes a holding unit configured to hold a first address conversion table for wear leveling of a first block of the non-volatile memory, a second address conversion table for wear leveling of a second block other than the first block of the non-volatile memory, and a third address conversion table for wear leveling of a third block other than the first block of the non-volatile memory; and a writing unit configured to write, in the first block, a replication of the second address conversion table in addition to one replication of the first address conversion table and to write, in the third block, another replication of the first address conversion table in addition to a replication of the third address conversion table.

Writing an address conversion table for nonvolatile memory wear leveling

The present invention provides a computer system including a CPU with an L2 cache, a bus master device and a bus slave device. They are connected via a system bus to communicate with each other. The computer systemincludes: a transaction monitorfor monitoring first transaction states TrC-TrCn between a CPUand an L2 cache, and second transaction states from TrBto TrBn between a system busand the L2 cache, between the system busand a bus master deviceor between the system busand bus slave devices; and a clock generatorable to change the frequency FreqC-FreqSof the clock of the CPU, the system bus, and the bus slave devicesaccording to the first transaction and second transaction states received from the transaction monitor

Power saving based on clock management claim of priority

The present invention provides a computer system including a CPU and a memory subsystem connected via a system bus to communicate with each other. The computer systemincludes a bus monitorconnected to the system busto monitor the frequency of access requests from the CPUto the memory subsystem, and a latency changing meansfor sending a control signal to the memory subsystem to change the latency of the access requests in response to the frequency of the access requests received from the bus monitor.

The present invention relates to a memory system including a memory cell array and being connected to an address input, a command input, and a data input/output, said memory system including latching circuits (RALTH and WALTH) for latching a read address and a write address being inputted from the address input, an address selection circuit (ACOMSEL) for selecting, as an access address, any one of the read address and the write address being latched in the latching circuits, a read latching circuit (PFLTH) for latching a read data being read from the memory cell array, a write latching circuit (DINLTH) for latching a write data being inputted from the data input/output and a control circuit (ACTL) for controlling the access address being selected by said address selection circuit in response to a command being inputted from said command input, said control circuit for controlling, if the memory cell corresponding to said selected access address is activated and further said selected access address is a write address, a timing of writing the write data being latched by said write latching circuit into the activated memory cell.

Method of controlling memory and memory system thereof

Wireless data communication method and apparatus using two electromagnetic signals having different polarizations. Codes related to relative values of the amplitudes of the two signals are generated in correspondence with data to be transmitted. The signals are modulated according to the codes using phase shift keying and amplitude shift keying. The amplitude shift keying modulates the two electromagnetic signals by changing the difference between their two amplitudes in accordance with data encodings. The two signals are transmitted to receiver, which decodes the phases and relative amplitudes to obtain the codes, and reproduces the data from the obtained codes.

Polarization modulation with amplitude differential

A startup system using a boot code includes an external memory storing a boot code, a buffer connected to an external memory for storing the boot code transferred from the external memory, a DMA controller for commanding transfer of the boot code from the external memory to the buffer, and a mapping circuit connected to the buffer for mapping the boot code stored in the buffer onto a CPU. Accordingly, a flash ROM for storing the boot code may be eliminated, thereby reducing system cost.

Startup system and method using boot code

Disclosed is a method, system, and data structures for updating data in a storage device. An update to one or more blocks of customer data at addresses in the storage device is received. For each block of data to update, metadata is generated indicating the address of the block in the storage device and an error checking code that is capable of being used to determine whether the customer data in the block has changed. For each block of data to update, the block of data to update and the metadata for the block are written to cache. Further, for each block of data to update, the block of data and the metadata are transferred for the block from the cache to the storage device. The metadata may be used during power loss and recovery.

Method, system, and data structures for using metadata in updating data in a storage device

A memory module is described having a memory array storing data, an ID information output circuit for outputting ID information for identifying memory modules, and output switching means for selectively switching between output from the memory array and output from the ID information output circuit, and output from the ID information output circuit will be selected instead of output from the memory array until the memory module is initially written after the power supply to the memory module has been started. This enables a memory module to be identified without having to add parts to a computer system unit or providing a ROM storing a specification or the like to the memory module.

Memory module self identification

The present invention is directed to a microprocessor (MPU) 10 comprising a bridge chip including a bus retry output part ( ) for outputting a bus retry (BRTY) signal; a bus retry detection part ( ) for determining whether a bus retry signal is input from the bridge chip ; and a bus cycle controller ( ) for suspending a currently executed bus cycle in response to detection of the bus retry signal and for re-starting the suspended bus cycle. The bridge chip also preferably includes an interrupt detection part ( ) for determining whether another process request is issued during suspension of the bus cycle; and an interrupt controller ( ) for executing that other process before re-starting the suspended bus cycle.

System for suspending current bus cycle of microprocessor upon receiving external bus retry signal for executing other process and re-staring the suspended bus cycle thereafter

Disclosed is a method, system, program, and data structures for transferring data to a requesting application. A request is received for one or more blocks of data at contiguous addresses in a storage device. Each block of data includes customer data and metadata indicating the address of the block in the storage device and an error checking code that is capable of being used to determine whether the customer data in the block has changed. For each requested block, a determination is made as to whether the address of the block of data in the metadata and the requested address match. Further, for each requested block, an operation is performed on the customer data in the block and the error checking code to determine whether the customer data has changed. The requested block is transferred to the requesting application if the address of the block in the metadata and requested address match and the customer data has not changed.

Growing community of inventors

Shiga-ken, Japan

Norio Fujita