Hitachi, Ltd.

Renesas Technology Corp.

Japan Aviation Electronics Industry, Limited

Opnext Japan, Inc.

Renesas Electronics Corporation

Hitachi Metals, Ltd.

Hitachi Cable, Inc.

Hitachi Vantara Corporation

Other

Hitachi High-Tech Electronics Engineering Co., Ltd.

Norio Chujo

Masami Makuuchi

Ritsuro Orihashi

Yoshihiko Hayashi

Kengo Imagawa

Masayoshi Takahashi

Keiichi Yamamoto

Naoki Matsushima

Yasunobu Matsuoka

Masayoshi Yagyu

Satoshi Muraoka

Akio Osaki

Yuichi Koreeda

Yutaka Uematsu

Toshiki Sugawara

Madoka Minagawa

Hisaaki Kanai

Naohiko Baba

Rika Nomura

Yoshitomo Arai

Saori Hamamura

Satoshi Kaneko

Yoshinori Sunaga

Tsutomu Kono

Shuuichi Kariyazaki

Kazuyuki Nakagawa

Kinya Yamazaki

Koji Nakagawa

Toshiaki Takai

Toru Yazaki

Keita Tsuchiya

Shinji Homma

Ritsurou Orihashi

Takehito Kamimura

Yasuhiro Yamada

Kentaro Shimada

Osamu Kagaya

Yoshiaki Sato

Tatsuya Saito

Atsushi Hasegawa

Koichiro Adachi

Yasuhiro Ikeda

Masanori Takada

Yoshiaki Ishigami

Wen Zheng Li

Hiroki Yamashita

Masataka Sato

Hidehiro Toyoda

Hideo Arimoto

Takashi Kumakura

Katsunori Hirano

Tadashi Hatano

Takeshi Yamashita

Yosuke Ishimatsu

Takayuki Nakao

Tetsuya Aoki

Hideyuki Serizawa

Akihiro Hayami

Kazuo Ishiyama

Yosuke Katsura

Tsuneo Kawamata

Tomoaki Shimotsu

Kohji Nakagawa

Yoshiharu Umemura

Shinji Katayama

Kaoru Arita

Masahiro Imanari

Atsushi Obuchi

A storage apparatus includes a first control device having a first memory, a second control device having a second memory, and a memory module having a third memory. The first memory and the second memory store drive control information including association between a logical address and a physical address, cache data in data I/O processing, and cache control information including association between a logical address of the cache data and a cache address of the cache data. The third memory stores the drive control information, dirty data of the cache data in the first memory, dirty data of the cache data in the second memory, and the cache control information. Even in a case where the control device or the memory module is blocked, the dirty data is set to be redundantly stored in each of different apparatuses.

Storage apparatus and control method for storage apparatus

A storage apparatus includes a first controller having a first memory, a second controller having a second memory, and a memory module having a third memory. The first memory stores drive control information including a correspondence between a logical address and a physical address, first cache data in a data input-output (I/O) process, and first cache control information including a correspondence between a logical address and a cache address of the first cache data. The second memory stores drive control information, second cache data in the data I/O process, and second cache control information including a correspondence between a logical address and a cache address of the second cache data. The third memory stores first cache data provided with redundancy and second cache data provided with redundancy.

A storage system having a plurality of control units that perform read control of data stored in a storage and write control of the data, the storage system comprising, each of the plurality of control units has a processor, a first memory connected to the processor and storing software for executing a process of read control and write control, a network interface for connecting to a control unit network that connects each of the plurality of control units, and a second memory connected to the network interface and storing control information of the data subject to read control and write control and cache data of the storage.

Storage system having control units to perform data control and method of performing data control in the storage system

A wiring substrate is connected to a backplane, and includes: a first connector that is mounted on one surface of the wiring substrate and is connected to the backplane; an opening portion that is formed in the one surface on a side opposite to a side connected to the backplane of the first connector, and through which a cable having one end connected to the first connector is passed; an integrated circuit that is mounted on the one surface on a side opposite to a side on which the first connector is present relative to the opening portion; and a second connector that is mounted on the other surface on a side opposite to the one surface in the vicinity of the integrated circuit on the side opposite to the side on which the first connector is present relative to the opening portion, is connected to the integrated circuit via a through hole penetrating the wiring substrate, and is connected to the other end of the cable.

Wiring substrate and information processing device

A storage system includes a CPU, a first memory module, a second memory module, and a storage device. The processor and the first memory module are installed in the same node. The second memory module are replaceable without shutting down power supply of the node. The first memory module stores an operating system and a program for managing user data to be stored in the storage device. The second memory module stores cache data of the user data to be stored in the storage device. The processor is configured to store a copy of data to be stored in the second memory module in the third memory module.

Storage system and method for minimizing node down time

In a multilayer wiring board having through holes used in an electronic device, wiring is efficiently performed at high density while preventing crosstalk of differential signals. A wiring board includes: a plurality of pads arranged linearly at a predetermined pitch; a plurality of through holes arranged in parallel along an arrangement direction of the pads; and a wiring pattern connecting the pad to the through hole. Between the through holes connected to the pads which are connected to the ground via the wiring patterns, two through holes through which each of a pair of differential signals constituting a differential signal pair passes are provided such that a direction of a straight line connecting the two through holes is inclined to the arrangement direction of the pads.

Wiring board and electronic device

Performance of a semiconductor device is improved. The semiconductor device includes a semiconductor chip and a chip component that are electrically connected to each other via a wiring substrate. The semiconductor chip includes an input/output circuit and an electrode pad electrically connected to the input/output circuit and transmitting the signal. The chip component includes a plurality of types of passive elements and includes an equalizer circuit for correcting signal waveforms of the signal, and electrodes electrically connected to the equalizer circuit. The path length from the signal electrode of the semiconductor chip to the electrode of the chip component is 1/16 or more and 3.5/16 or less with respect to the wavelength of the signal.

Semiconductor device

A semiconductor device includes a semiconductor chip mounted over a wiring substrate. A signal wiring for input for transmitting input signals to the semiconductor chip and a signal wiring for output for transmitting output signals from the semiconductor chip are placed in different wiring layers in the wiring substrate and overlap with each other. In the direction of thickness of the wiring substrate, each of the signal wirings is sandwiched between conductor planes supplied with reference potential. In the front surface of the semiconductor chip, a signal electrode for input and a signal electrode for output are disposed in different rows. In cases where the signal wiring for output is located in a layer higher than the signal wiring for input in the wiring substrate, the signal electrode for output is placed in a row closer to the outer edge of the front surface than the signal electrode for input.

Provided is a configuration of a driver integrated circuit that can output a voltage exceeding the withstand voltage of a process, and that satisfies required apparatus performance (high speed and high voltage). A differential input circuit, a level shift circuit, and an output circuit are manufactured by the same process and divided and disposed on three or more chips with different substrate potentials (sub-potentials). By setting different applied voltages to the substrates of the chips, an output voltage greater than the process withstand voltage can be provided (see FIG.).

Driver integrated circuit

The present invention achieves a way of mounting plural optical modules onto a wiring board more simply and more densely. There is provided an optical module assembly for mounting plural optical modules onto a wiring board. The optical module assembly includes the optical modules to which optical wiring has been connected and a module case to accommodate the optical modules. The optical modules and the module case are unified. The module case is provided with a floating mechanism for making the optical modules floating, when accommodated therein. The floating mechanism is comprised of plate springs or the like.

Optical module assembly, optical wiring board, and information processing device using them

There is provided a photoelectric conversion module that can be mounted two-dimensionally over a device board in a high-density, low-height manner and cooled efficiently with an easy-to-install collective-type radiator. In the photoelectric conversion module mounted over the device board, an optical connector is attached to that surface of an optical subassembly facing the device board. An electric connector has at least two sides thereof opened so that the optical transmission medium is threaded therethrough and extended through at least two facing sides of the optical subassembly. The optical transmission medium is thus extended between the optical subassembly and the device board in a vertically stacked manner.

Photoelectric conversion module and transmission apparatus using the same

A backplane optical connector includes a first connector secured to a backplane and a second connector mounted on a daughter board. The first connector includes a first optical input-output part, guide holes, and a shutter. The shutter is a plate that covers the first optical input-output part when the daughter board is not inserted. The second connector includes guide pins, a pressing part, and a second optical input-output part. The guide pins first make contact with the first connector and are inserted into the guide holes. The pressing part pivots the shutter after degrees of freedom of the second connector are restricted by the guide pins and the guide holes. There is a space for accommodating the pivoted shutter between the pressing part and the second optical input-output part. The pressing part does not make contact with the first connector until the pressing part makes contact with the shutter.

Backplane optical connector

Housing for a connector

A circuit having a sensor with a stray capacitance value. An output from the sensor is connected to the input of an amplifier while a negative capacitance circuit is electrically connected in parallel with the sensor output. The negative capacitance circuit reduces the effect of the sensor stray capacitance to provide an increased bandwidth and decreased noise on the amplifier output.

Wideband low noise sensor amplifier circuit

Growing community of inventors

Tokyo, Japan

Norio Chujo