Kabushiki Kaisha Toshiba

Kioxia Corporation

Toshiba Memory Corporation

Norio Aoyama

Ryuji Nishikubo

Hiroki Matsudaira

Yoshihisa Kojima

Mitsunori Tadokoro

Kazuaki Takeuchi

Shinji Yonezawa

Aurelien Nam Phong Tran

Mel Stychen Sanchez Tan

Eiji Yoshihashi

Masahiro Ogawa

Yasunori Arai

According to one embodiment, a semiconductor storage device includes a volatile memory, nonvolatile memory chips, channels, nonvolatile memory interfaces, and a bus arbiter. Each of the channels is connected to at least one nonvolatile memory chip of the nonvolatile memory chips. Each of the nonvolatile memory interfaces is connected to at least one channel of the channels and controls the at least one nonvolatile memory chip via the connected channel. The bus arbiter controls use of a bus in data transfer between the volatile memory and each of the nonvolatile memory chips in accordance with a bandwidth of the bus.

Semiconductor storage device

According to one embodiment, a memory system includes: a memory device to store data; and a controller to control an operation for the memory device. The memory device executes a program operation by a first program voltage on memory cells belonging to a first address of the memory device; detect at least one first memory cell among the memory cells by using a first determination level and a second determination level different from the first determination level, the at least one first memory cell having a threshold voltage of a value different from a value between the first determination level and the second determination level; and generate unique information of the memory device, based on a position of the first memory cell in the first address.

Memory system, memory device, and control method of memory system for generating information from a threshold voltage

A memory system includes a nonvolatile memory and a controller that performs first, second, and third processes on memory cells of the nonvolatile memory. The first process is performed on first memory cells to store a first value therein, such that a highest threshold voltage among the threshold voltages of the first memory cells is set as a first threshold voltage. The second process is performed on second memory cells to store a second value therein, such that a lowest threshold voltage among the threshold voltages of the second memory cells is set as a second threshold voltage higher than the first threshold voltage. The third process performed on third memory cells such that a lowest threshold voltage in the third memory cells is lower than the first threshold voltage, and a highest threshold voltage in the third memory cells is higher than the second threshold voltage.

Memory system

According to one embodiment, a memory system includes a semiconductor memory device including a first and second string each including cells coupled in series, and a memory controller configured to instruct the device to execute a write operation for writing data on any one of the cells in the first or second string. The first and second string are coupled in parallel between a bit line and a source line, and coupled to different word lines. The write operation includes a first write operation and a second write operation executed after the first write operation. The controller is configured to instruct the device to execute a first write operation on a second cell in the second string between a first write operation on a first cell in the first string and a second write operation on the first cell.

Memory system and control method of memory system for controlling of first and second writing operations

According to one embodiment, a memory system writes data to a first block, and executes a garbage collection when the number of free blocks is not greater than a first threshold value. The memory system calculates a first number which is a ratio of the number of copy destination blocks needed for the garbage collection to the number of blocks to which data designated by a write command is written. The memory system determines whether the first number is greater than a second threshold value when a first command is received from the host, and performs fill-up processing for the first block when the first number is not greater than the second threshold value.

Memory system and control method of the same

A memory controller according to the embodiment includes a front-end unit that issues an invalidation command in response to a command from outside of the memory controller, the command including a logical address, an address translation unit that stores a correspondence relationship between the logical and a physical address, an invalidation command processing unit that, when the invalidation command is received, registers the logical address associated with the invalidation command as an invalidation registration region in an invalidation registration unit and issues a notification to the front-end unit, and an internal processing unit that dissolves a correspondence relationship between the logical address registered in the invalidation registration unit and the physical address in the address translation unit in a predetermined order by referencing the logical address registered in the invalidation registration unit. The front-end unit transmits completion command which indicates the completion of the command in response to the notification.

Memory controller and memory system

According to one embodiment, a memory system includes a nonvolatile memory including a plurality of blocks, and a controller controlling the nonvolatile memory. The controller cyclically executes patrol read, the patrol read including reading data and testing the read data, the read data being data of pages connected to some of word lines in each of the blocks of the nonvolatile memory.

Memory system and method of controlling memory system

According to one embodiment, when loading of reverse lookup information from a nonvolatile first memory to a randomly accessible second memory has failed, a controller determines whether data at a first physical address is valid or invalid by using lookup information loaded from the first memory to the second memory.

A controller performs a coding process based on a first frame including data of a plurality of pages connected to first word lines being a predetermined number of consecutive word lines in a block, and performs, when padding data is written to a plurality of pages connected to second word lines being the predetermined number of word lines subsequent to the first word lines, the coding process based on a second frame obtained by excluding the padding data from a frame including data of the pages connected to the second word lines.

Growing community of inventors

Machida, Japan

Norio Aoyama