Kawasaki Steel Corporation

Kawasaki Microelectronics, Inc.

Norimitsu Sako

Hideyuki Kitayama

Keiichi Kawana

Toshikazu Ishii

A method and an apparatus for driving passive matrix liquid crystal, comprising the steps of: simultaneously selecting Y row electrodes, where Y is an odd number of 7 and above; calculating an exclusive OR between a Y-bit row selection vector representing a selection pattern of the Y row electrodes and Y-bit ON/OFF display data representing a display pattern of column electrodes, for each corresponding bit; adding the exclusive ORs for each bit; when X=(Y+1)/2, and a 1/(X&#x2212;1) voltage of the maximum voltage of the column electrodes is Vc, selecting a voltage level of the column electrodes from X voltage levels satisfying: [2&#xd7;i&#x2212;(X&#x2212;1)]&#xd7;Vc (i=an integer of 0 to (X&#x2212;1)) in accordance with the result of the addition for driving. These method and apparatus prevent the frame response phenomenon of high-speed liquid crystal while realizing high-contrast display, low-voltage driving, low power consumption, and reduction in chip size.

Method and apparatus for driving passive matrix liquid crystal

A method and an apparatus for driving passive matrix liquid crystal, comprising the steps of: simultaneously selecting Y row electrodes, where Y is an odd number of 7 and above; calculating an exclusive OR between a Y-bit row selection vector representing a selection pattern of the Y row electrodes and Y-bit ON/OFF display data representing a display pattern of column electrodes, for each corresponding bit; adding the exclusive ORs for each bit; when X=(Y+1)/2, and a 1/(X&#x2212;1) voltage of the maximum voltage of the column electrodes is Vc, selecting a voltage level of the column electrodes from X voltage levels satisfying:[2&#xd7;i&#x2212;(X&#x2212;1)]&#xd7;Vc (i=an integer of 0 to (X&#x2212;1)) in accordance with the result of the addition for driving. These method and apparatus prevent the frame response phenomenon of high-speed liquid crystal while realizing high-contrast display, low-voltage driving, low power consumption, and reduction in chip size.

A method of designing a logic circuit including pass transistors is disclosed. A logic group having a complementary variable in a given logical expression to be realized into the logic circuit is mapped using a multiplexer composed of a combination of the pass transistors. The number of transistors used in the logic circuit and the number of stages can be reduced by taking advantage of the multiplexer. When a logic circuit including both pass transistors and a multiple-input logic gate is designed, a logic group having a common variable in the given logical expression is mapped using the multiple-input logic gate. The number of transistors used in the logic circuit and the number of stages can be further reduced by taking advantage of the multiple-input logic gate. In order to ease the above mapping procedure, a complementary variable is identified and the given logical expression is optimized by grouping product terms of the logical expression by the complementary variable. Furthermore, a common variable is identified, and the logical expression is further optimized by grouping product terms of the logical expression by the common variable.

Pass-transistor logic circuit and a method of designing thereof

A CMOS image sensor includes a plurality of pixel sensors arranged in a two-dimensional array. In each pixel sensor, a signal corresponding to the absolute value of the amount of incident light with reduced reset noise is obtained. The signals of the respective pixel sensors are then output in a block scanning fashion. The CMOS image sensor does not need to include a preprocessing circuit for discrete cosine transform or a high-capacity frame memory for raster scanning.

CMOS image sensor having block scanning capability

The invention obtains a pattern output signal with a minimal delay time and to reduce the size of a circuit substantially. The data output from the memory is decoded and then the decoder outputs the decoded signal. Next, the pattern selection output signal is output in accordance with the decoded signal and a pattern information signal to control an ON/OFF ratio by timesharing by the pattern selection circuit. The delayed clock signal of the clock signal is generated by the delayed clock signal generating circuit, and then the pattern selection output signal is held in synchronization with the holding signal that is the difference between the clock signal and the delayed clock signal, and is output as the pattern output signal by the temporary holding circuit.

Pattern output circuit and pattern output method

Pass transistor logic circuit and a method of designing thereof

A semiconductor integrated circuit is constructed with composite pass-transistor logic circuits serving as elementary circuit units each including a plurality of pass-transistor logic trees and a multiple-input logic gate. A wide variety of logical operations, even complex opearations, can be efficiently expressed using the composite pass-transistor logic circuit, and the resultant logic circuit can operate at a high speed. Thus, the semiconductor integrated circuit of the present invention can realize various logic functions required for various users in an efficient fashion. The present invention is particularly useful when applied to a field-programmable gate array integrated circuit, since complex logical operations can be expressed in a simple and efficient fashion by the composite pass-transistor logic circuits. The gate array integrated circuit obtained in accordance with the present invention can operate at a high speed with low power consumption. The present invention also discloses a basic cell suitable for use in an integrated circuit in the form of a gate array, and more particularly, a programmable logic block for use in a field programmable gate array integrated circuit.

Semiconductor integrated circuit capable of realizing logic functions

A logic circuit combines a plurality of pass-transistor logic trees and a multiple-input logic gate for receiving intermediate logic signals from the respective pass-transistor logic trees, and can express a complex logical operation while decreasing the number of stages in pass-transistor logic trees and improving operation speed. Even a logical operation that cannot be expressed efficiently by a known or conventional pass-transistor logic circuit can be expressed efficiently with performance higher than that of a known CMOS logic circuit. Furthermore, when a static feedthrough current of the multiple-input logic gate is suppressed, power consumption can be reduced. In some embodiments, since circuitry for suppressing a static feedthrough current of the multiple-input logic gate is arranged so that a probability of occurrence of logical collision with a preceding stage will decrease or will be nil, power consumption can further be reduced.

Logic circuit utilizing pass transistors and logic gate

A semiconductor device has a constant-current circuit selectively operative in an operation mode among a writing mode in which a writing current for causing the antifuse to change in state from a breaking state to a conductive state is supplied to the antifuse, a sense mode in which a sensing current for detecting a state of the antifuse is supplied to the antifuse, and an additional writing mode in which an additional writing current for performing an additional writing is supplied to the antifuse which is subjected to writing.

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Chiba, Japan

Norimitsu Sako