Pioneer Electronic Corporation

Pioneer Video Corporation

Norimichi Katsumura

Kazuo Watanabe

Yoshinobu Takamura

Yukio Matsumoto

Kazuhiro Hayashi

Hiroyuki Ishihara

Makio Yamaki

Nobuhiko Osawa

Toshiyuki Naoe

Nebuhiko Osawa

An audio signal data processing system comprises input device for sequentially supplying an audio signal data, data memory control device for writing the audio signal data into a data memory and reading-out the data from the data memory, delay memory control device for sequentially reading-out the audio signal data from the data memory and storing the data into a location of a delay memory indicated by a writing address and for reading-out the audio signal data from a location of the delay memory indicated by a reading address and writing the data into the data memory, address designating devices for designating the writing and reading addresses, arithmetic device for multiplying a predetermined coefficient data to the audio signal data having been read-out by the delay memory control device and written into the data memory, and output device for providing the audio signal data in accordance with a result of operation by the arithmetic device. The data memory control device and the delay memory control device write and read the audio signal data into and from the data memory through data buses independent from each other.

Audio signal processing system having independent and distinct data

A muting control circuit is provided in which muting is performed when any one of a plurality of unlock detection signals is detected, indicating circuits is unlocked or when a data error is detected in a demodulator. In this way, reading time can be shortened to the minimum time required for muting. In addition, when one unlock detection circuit is triggered due to a disorder in the input, the unlock detection signal is provided immediately, so that the muting control signal is supplied and muting can be performed even when there is a time delay before the unlock detection circuit detects an unlocked state.

Muting control circuit

A demodulation clock generator circuit employed in a modulation system such as a bi-phase mark system is improved by including a frequency detector to speed up the initial processing of a data signal to be demodulated. The frequency detector generates a frequency detection signal which corresponds to a signal from an oscillator and a signal from a synchronization signal portion of the signal to be demodulated. The frequency detector includes a memory portion clocked by the oscillator for storing the states of the signal to be demodulated and a signal generating portion for supplying the frequency detection signal when information stored in the memory portion is the same as a synchronizing portion of the signal to be demodulated and has a frequency of less than a predetermined value.

Demodulation clock generator circuit

Growing community of inventors

Yamanashi, Japan

Norimichi Katsumura