Kabushiki Kaisha Toshiba

Seiko Kabushiki Kaisha

Noriko Inoue

Takehiko Okuyama

Shinichi Yasuda

Atsushi Shimbo

Tetsufumi Tanamoto

Kouki Uesugi

Yusuke Sugiura

Akira Tomita

Ryusuke Murakami

According to one embodiment, a random number generating circuit includes first to N-th oscillating circuits (N is a natural number equal to 2 or greater), first to N-th latch circuits that latch outputs of the first to N-th oscillating circuits by a first clock having a first frequency, first to N-th exclusive OR circuits, (N+1)-th to (2&#xd7;N)-th latch circuits that latch outputs of the first to N-th exclusive OR circuits by the first clock, an (N+1)-th exclusive OR circuit that outputs an exclusive OR of outputs of the (N+1)-th to (2&#xd7;N)-th latch circuits, and an M-bit shift register that converts serial data output from the (N+1)-th exclusive OR circuit into M-bit parallel data (M is a natural number equal to 2 or greater) by a second clock having a second frequency.

Random number generating circuit

A method for transmitting information included in a received packet to an upper layer of a node, including: judging whether or not a first packet satisfies a first condition, storing information which is information in the first packet and used as a part of or all of a second condition when the first packet is judged to satisfy the first condition, judging whether or not a second packet satisfies the second condition when the first packet is judged not to satisfy the first condition, and enabling information in the second packet to be transmitted to the upper layer of a node when the second packet is judged to satisfy the second condition.

Method and apparatus for transmitting to an upper layer of information included in a packet

A FIFO control circuit for passing receive data and transmit data in a first-in first-out system, respectively, is provided. The FIFO control circuit comprises a receiving circuit; a transmitting circuit; a FIFO buffer for temporarily storing receive data received by the receiving circuit and transmit data to be transmitted by the transmitting circuit; a free space management circuit for managing free space of the FIFO buffer; a first address storage unit for storing an address range in which the receive data is stored in the FIFO buffer; a second address storage unit for storing an address range in which the transmit data is stored in the FIFO buffer; a write pointer control circuit writing the receive data and the transmit data; and a read pointer control circuit reading out the receive data and the transmit data from the FIFO buffer.

FIFO control circuit

On the basis of information of a topology map, a parent node ID list is generated to show correspondence of ID of each node to that of its parent node. Information given by the parent node ID list is transmitted as connection display data in a predetermined format. The receiving side, on the basis of the received connection display data, obtains information of a connecting status display to display connecting status of a network. On the basis of this information, a display to show connecting status of the network is displayed.

Apparatus for transmitting connecting status and method of displaying connecting status

When an error is detected in a received packet, a higher application is informed that the error occurred, and when no error is detected in the received packet, the higher application is informed that the packet has been received. If a next packet is received while a packet having the detected error is stored in a data storing region, an acknowledge signal indicating that the packet cannot be received is sent to a source node, and the packet having the detected error stored in the data storing region is invalidated by a request from the higher application. When the error is detected in a received packet, that packet stored in the data storing region is invalidated.

Growing community of inventors

Tokyo, Japan

Noriko Inoue