Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Elpida Memory, Inc.

Hitachi Ulsi Systems Co., Ltd.

Other

Nec Corporation

Nec Electronics Corporation

Norikatsu Takaura

Hideyuki Matsuoka

Motoyasu Terao

Kenzo Kurotsuchi

Riichiro Takemura

Yoshitaka Sasago

Masaharu Kinoshita

Nozomu Matsuzaki

Satoru Hanzawa

Takahiro Morikawa

Yuichi Matsui

Akio Shima

Tomio Iwasaki

Naoki Yamamoto

Ryo Nagai

Yoshihisa Fujisaki

Kazuhiko Kajigaya

Takeshi Sakata

Tomonori Sekiguchi

Tsuyoshi Yamauchi

Kenichi Osada

Takashi Kobayashi

Satoru Yamada

Shinichiro Kimura

Kousuke Okuyama

Masahiro Moniwa

Akio Nishida

Kota Funayama

Osamu Tonomura

Takayuki Kawahara

Hitoshi Kume

Toshiyuki Mine

Hiroshi Moriya

Mitsuharu Tai

Hisao Asakura

Minoru Ogushi

Kiyoo Itoh

Yoshinobu Kimura

Tsugio Takahashi

Kiyonori Oyu

Naohiko Irie

Masayuki Nakamura

Kenichi Akita

Ryoichi Nakamura

Tomoyuki Kodama

Nobuyuki Arasawa

Takasumi Oyanagi

Masahito Kitamura

Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line () which is provided above the substrate; a first laminated body, which is disposed above the first word line (), and which has the N+1 (N&#x2267;1) number of first inter-gate insulating layers (-) and the N number of first semiconductor layers (-) alternately laminated in the height direction of the substrate; a first bit line (), which extends in the direction that intersects the first word line (), and which is disposed above the laminated body; a first gate insulating layer () which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (-) and those of the N number of the first semiconductor layers (-); a first channel layer () which is provided on the side surface of the first gate insulating layer (); and a first variable resistance material layer () which is provided on the side surface of the first channel layer. The first variable material layer () is in a region where the first word line () and the first bit line () intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.

Semiconductor storage device and method for manufacturing same

A superlattice phase change memory capable of increasing a resistance in a low resistance state is provided. The phase change memory includes a first electrode, a second electrode provided on the first electrode, and a phase change memory layer having a superlattice structure between the first electrode and the second electrode, the superlattice structure including to repeatedly formed layers of SbTeand GeTe. The phase change memory layer having the superlattice structure includes a SbTelayer containing Zr in contact with the first electrode.

Superlattice phase change memory including Sb2Te3 layers containing Zr

Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.

Semiconductor memory

Disclosed are a semiconductor storage device and a manufacturing method. The storage device has: a substrate; a first word line above the substrate; a first laminated body above the first word line and having N+1 first inter-gate insulating layers and N first semiconductor layers alternately laminated; a first bit line above the laminated body and extending in a direction that intersects the first word line; a first gate insulating layer on side surfaces of the first inter-gate insulating layers and the first semiconductor layers; a first channel layer on the side surface of the first gate insulating layer; and a first variable resistance material layer on the side surface of the first channel layer. The first variable resistance material layer is in a region where the first word line and the first bit line intersect. A polysilicon diode is used as a selection element.

On an insulating film () in which a plug () as a lower electrode is embedded, a laminated layer pattern of an insulating film () made of tantalum oxide, a recording layer () made of Ge&#x2014;Sb&#x2014;Te based chalcogenide to which indium is introduced and an upper electrode film () made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film () between the recording layer () and the plug (), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer () can be achieved. Further, by using the Ge&#x2014;Sb&#x2014;Te based chalcogenide to which indium is introduced as the recording layer (), the difference in work function between the insulating film () and the recording layer () is increased, and the programming voltage of the phase change memory can be reduced.

Semiconductor device

Provided is a nonvolatile memory device including a phase-change memory configured with cross-point memory cells in which memory elements formed of a phase-change material and selection elements formed with a diode are combined. A memory cell is configured with a memory element formed of a phase-change material and a selection element formed with a diode having a stacked structure of a first polycrystalline silicon film, a second polycrystalline silicon film, and a third polycrystalline silicon film. The memory cells are arranged at intersection points of a plurality of first metal wirings extending along a first direction with a plurality of third metal wirings extending along a second direction orthogonal to the first direction. An interlayer film is formed between adjacent selection elements and between adjacent memory elements, and voids are formed in the interlayer film provided between the adjacent memory elements.

Nonvolatile memory device and method of manufacturing the same

On the same semiconductor substrate, a memory cell array in which a plurality of memory elements R having a chalcogenide-material storage layerstoring a high-resistance state with a high electric resistance value and a low-resistance state with a low electric resistance value by a change of an atom arrangement are disposed in a matrix is formed in a memory cell region mmry, and a semiconductor integrated circuit is formed in a logic circuit region lgc. This chalcogenide-material storage layeris made of a chalcogenide material containing at least either one of Ga or In of 10.5 atom % or larger to 40 atom % or smaller, Ge of 5 atom % or larger to 35 atom % or smaller, Sb of 5 atom % or larger to 25 atom % or smaller, and Te of 40 atom % or larger to 65 atom % or smaller.

There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.

Semiconductor storage device

A recording layermade of a chalcogenide material which stores a high-resistance state of a high electrical resistance value and a low-resistance state of a low electrical resistance value is used as a memory element RM in a memory cell region, and it is formed so that a concentration of Ga or In of a first layerpositioned on a lower electrode TP side of the recording layeris higher than the corresponding concentration of a second layerpositioned on an upper electrodeside. For example, the recording layer is formed so that a content of Ga or In of the second layer is 5 atomic % or more smaller than that of the first layer. Also, a circuit which can reverse the voltage polarity between the upper electrode and the lower electrode in a set operation and a reset operation is provided.

To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.

Growing community of inventors

Tokyo, Japan

Norikatsu Takaura