Sony Corporation

Sony Semiconductor Solutions Corporation

Norihito Suzuki

Yusuke Tanaka

Hidekazu Kikuchi

Noboru Sasho

Tetsuya Fujiwara

Nobuhisa Ozawa

The object is to simplify the configuration of a filter in a reception apparatus. The reception apparatus includes a filter. The filter provided in the reception apparatus selects a signal transmission characteristic that is one of a band stop characteristic or a low pass characteristic. Further, selection of the signal transmission characteristic in the filter provided in the reception apparatus is performed in response to a desired signal and an interference signal. In the filter provided in the reception apparatus, passage of the desired signal and attenuation of the interference signal based on the selected signal transmission characteristic are executed.

Reception apparatus and reception method

Provided is a phase locked loop circuit that includes: a phase comparison section configured to compare a phase of a first clock signal and a phase of a second clock signal; a loop filter configured to generate a control voltage based on a comparison result by the phase comparison section; and a clock signal generation section configured to generate a clock signal having a frequency corresponding to the control voltage, and output the clock signal as the second clock signal. The loop filter includes a first resistor inserted between a first node on a signal path and a second node, a first capacitor inserted between the second node and a first DC power supply, a first switch inserted between the second node and a third node on the signal path, and a second capacitor inserted between the third node and a second DC power supply.

Phase locked loop circuit, phase locked loop module, and phase locked loop method

A circuit includes first and second capacitances arranged on a first path that connects first and second terminals; a first switch arranged between the first capacitance and the second capacitance; a second switch arranged on a second path that connects a reference voltage section and a first node formed between the first capacitance and the first switch; a third switch arranged on a third path that connects the section and a second node formed between the second capacitance and the first switch; a first resistance arranged on a fourth path that connects the first node and a third node formed between the first terminal and the first capacitance; a second resistance arranged on a fifth path that connects the second node and a fourth node formed between the second terminal and the second capacitance; a fourth switch on the fourth path; and a fifth switch on the fifth path.

Circuit, voltage control oscillator, and oscillation frequency control system

A voltage-controlled variable frequency oscillation circuit, includes: an oscillation circuit section including a resonance circuit which includes a coil and a variable capacitance element, and a negative resistance circuit; and a first resistor connected between the oscillation circuit section and a first one of a pair of terminals of a power supply.

Voltage-controlled variable frequency oscillation circuit and signal processing circuit

A charge pump circuit able to enhance the rising and falling characteristics of a current output, drive the current output with a short pulse, reduce leakage current at the OFF time when a current is not output, and realize a reduction of a power consumption and a PLL circuit using same. By outputting a charge current or a discharge current in accordance with an up signal or a down signal and turning on a third transistor (PC, NC) at the OFF time when the current is not output, an inverse bias voltage is supplied between a gate and a source of the second transistor (PA, NA), whereby a reduction of the leakage current can be realized. When the second or third transistor is switched in accordance with the up signal or the down signal, the timing of the control signal is appropriately controlled, simultaneous turning on of the second and third transistors can be avoided, release or injection of charges from and to the output terminal of the charge pump circuit can be prevented, and the stability of an oscillation frequency of a VCO can be improved.

Charge pump circuit and PLL circuit using same

A signal multiplexing circuit capable of reducing jitter provided with a first circuit for outputting input differential data by receiving a select drive signal comprising first and second NMOS transistors whose sources are commonly connected, a second circuit for outputting the input differential data with an inverted phase with respect to the output of the first circuit so as to add it to the output of the first circuit and never being selected by a select drive signal comprising third and fourth transistors whose sources are commonly connected, and a signal extracting circuit configured by connecting a connecting point of the sources of the first and second transistors to an output line of a select drive signal of a selector. As a result, jitter of the output signal can be reduced.

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Kanagawa, Japan

Norihito Suzuki