Fujitsu Corporation

Norihito Gomyo

Yasunobu Akizuki

Ryohei Okazaki

Ryuichi Sunayama

Takashi Suzuki

Toshio Yoshida

Aiichiro Inoue

Sota Sakashita

Yoshiteru Ohnuki

Atushi Fusejima

Atsushi Fusejima

A processing device performs a first process in a plurality of cycles to update a plurality of resources included in programmable resources. The processing device includes an instruction execution circuit that records that the first process is being executed, and makes an error notification when an error is detected during execution of an instruction, and a retry control circuit that records a type of the first process at a starting point of the first process, judges from the recorded type whether the first process is re-executable upon receiving the error notification during the first process, and instructs re-execution of the first process from a start of the first process in a case where the first process is judged to be re-executable. The instruction execution circuit performs a retry process to re-execute the first process when instructed from the retry control circuit to re-execute the first process.

Processing device and method of controlling processing device

A processing apparatus includes a processor. The processor stores a plurality of instruction codes, each of the plurality of instruction codes is a result of decoding of an instruction, selects an instruction code that is ready to be input from the stored instruction codes, when the selected instruction code is an operation instruction, uses for the processing, a register for processing corresponding to a write destination of the operation instruction, after detecting that operands to be used for the processing are ready, in the next cycle, issues a subsequent instruction, and when the selected instruction code is a memory access instruction, uses for the address calculation, the register, writes a processing result and load data that have been temporarily written in a buffer for register update from the buffer to the register at the time of instruction completion, after the completion of the memory access instruction, issues a subsequent instruction.

Processing apparatus and controlling method for processing apparatus

An arithmetic circuit performs a floating-point operation. A floating-point register includes entries each allocated to an architectural register or a renaming register. An operation execution controller circuit issues a floating-point operation instruction and outputs a termination report of the floating-point operation before the floating-point operation is terminated. When exception handling is not performed at the time of instruction completion even when an exception is detected in the operation of the floating-point operation instruction, an instruction completion controller circuit outputs a release instruction that indicates a release of a renaming register when instruction execution is completed after the termination report is received. An instruction decoder circuit receives the release instruction, allocates a first entry allocated to an architectural register that stores an execution result of the floating-point operation to a renaming register, and allocates a second entry allocated to a renaming register in the floating-point operation to the architectural register.

Releasing rename registers for floating-point operations

An arithmetic processing device includes a plurality of arithmetic processing units each including, an internal circuit that, in an instruction processing state in which an instruction is processed, processes the instruction and that, in an instruction processing stopped state in which instruction processing is stopped, transitions to a state of power save operation, and a power control circuit that disables the power save operation; and a monitoring circuit that monitors the instruction processing stopped state of the plurality of arithmetic processing units and counts the number of the arithmetic processing units in the instruction processing stopped state. The power control circuit of each of the plurality of arithmetic processing units disables the power save operation of the arithmetic processing unit in the instruction processing stopped state, in a case where the number of the arithmetic processing units in the instruction processing stopped state exceeds a threshold.

Arithmetic processing device and method of controlling arithmetic processing device

An arithmetic processing device includes: a branch prediction unit configured to predict a branch destination address and loop processing based on an address generated by an address generation unit; an instruction buffer unit configured to store an instruction of the address generated by the address generation unit; an instruction decoding unit configured to decode the instruction stored in the instruction buffer unit; and a loop buffer unit configured to store decoding results or decoding intermediate results of instructions of the predicted loop processing that are decoded by the instruction decoding unit and output the stored decoding results or decoding intermediate results a predetermined number of times in response to the loop processing, in which during a period when selecting the output of the loop buffer unit, operations of the address generation unit, the branch prediction unit, the instruction buffer unit, and the instruction decoding unit are stopped.

Arithmetic processing device for predicting loop processing

A prefetch request circuit is provided in a processor device. The processor device has hierarchized storage areas and can prefetch data of address to be used between appropriate storage areas among the storage areas, when executing respective instruction flows obtained by multi-flow expansion for one instruction at a time of decoding of the instruction. The prefetch request circuit includes a latch unit to hold, when a state in which the respective instruction flows to access the storage area are executed with a maximum specifiable data transfer volume is specified, the state during a time period of the multi-flow expansion; and a prefetch request signal output unit to output a prefetch request signal to request the prefetch every time when the instruction flow is executed, based on an output signal of the latch unit and a signal indicating an execution timing of the respective instruction flows.

Prefetch request circuit

A processor is provided that is capable of concurrently processing a sequence of instructions for a plurality of threads achieving the retry success rate equivalent to the success rate in processors that process a sequence of instructions for a single thread. An arithmetic deviceis provided with an instruction execution circuitfor executing a plurality of threads, or an execution control circuitfor controlling the execution state or rerunning of the threads.

Arithmetic device for concurrently processing a plurality of threads

A processor includes an accumulator, a storage that outputs data to the accumulator, an error detector that outputs a first error detection signal upon detecting an error in the data, an error identifier that outputs an error identification signal indicating that an error occurs in the storage, an error identification signal holder that outputs the error identification signal as a second error detection signal, an error detection signal holder that holds the first error detection signal and outputs a cancellation signal to stop the accumulation processing of the accumulator, a first calculator that starts making a first calculation based on the second error detection signal and the cancellation signal, and outputs a correction start signal after a lapse of a calculation period, and an error corrector that corrects the error of the data upon receiving the correction start signal.

Processor, information processing apparatus, and method of controlling processor

An arithmetic device simultaneously processes a plurality of threads and may continue the process by minimizing the degradation of the entire performance although a hardware error occurs. An arithmetic deviceincludes: an instruction execution circuitcapable of selectively executing a mode in which the instruction sequences of a plurality of threads are executed and a mode in which the instruction sequence of a single thread is executed; and a switch indication circuitinstructing the instruction execution circuitto switch a thread mode.

Arithmetic device for processing one or more threads

In the instruction control apparatus having an instruction processing suspension unit and an error detection unit, in order to improve the reliability of the apparatus, the apparatus is configured in such a way that when an error occurs to certain hardware resources in the instruction processing apparatus, error detection is conducted if instruction processing is under way, but error detection is deterred if instruction processing is in suspension, and the scope of the error which cannot be deterred during the suspension of instruction processing is made narrower than the scope of the error which cannot be deterred during instruction processing.

Hardware error control method in an instruction control apparatus having an instruction processing suspension unit

A parity generating circuit reverses generated parity data to detect a parity error of a CSE entry during a determination of completion to execute a command retry. A parity check circuit that detects a parity error requests for the execution of the command retry. When a command retry mechanism stops a program and interrupts a verification, the execution of the command retry is suppressed by assuming that no parity error is detected.

Information processing apparatus having command-retry verification function, and command retry method

A control reservation station stores the control information of a micro program to control one or more flows of an instruction process and controls each flow using the control information. A data buffer stores data to be used to control each flow and outputs the data at an appropriate timing.

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Kawasaki, Japan

Norihito Gomyo