Sony Corporation

Sony Semiconductor Solutions Corporation

Norihisa Shirota

Kaichi Yamamoto

Yoshitaka Hashimoto

Hiizu Ootorii

Haruo Togashi

Tetsujiro Kondo

Kenichi Sato

Takao Abe

Hideyuki Matsumoto

Yasunari Ikeda

Yasunobu Kato

Yasuhiro Iida

Seiichiro Iwase

Takao Yamazaki

Kazuo Yamagiwa

Noboru Oya

Shinji Takada

Michio Nagai

Mitsuru Sasano

An image pickup panel () includes: photodetection sections () each including a photodetector (-) and a receiver (-) which are integrally molded and having solder bumps () formed thereon, the photodetector converting received light into a current signal, the receiver converting the current signal into a voltage signal; and a wiring layer () including a wiring pattern installed therein and allowing the photodetection sections to be mounted thereon for respective pixels by the solder bumps, the wiring pattern being connected to the photodetection sections.

Image pickup panel and image pickup processing system

An image pickup panel () includes: photodetection sections () each including a photodetector (-) and a receiver (-) which are integrally molded and having solder bumps () formed thereon, the photodetector converting received light into a current signal, the. receiver converting the current signal into a voltage signal; and a wiring layer () including a wiring pattern installed therein and allowing the photodetection sections to be mounted thereon for respective pixels by the solder bumps, the wiring pattern being connected to the photodetection sections.

A wireless relay system () comprises a wireless camera () and a reception relay station (). The reception relay station () comprises a plurality of external reception units () arranged at spatially different positions and an internal reception unit (). Each reception section () in the internal reception unit () demodulates a signal received in the external reception unit () and outputs a transport stream. At this time, each reception section () sets an error indicator flag to 1 for a TS packet causing a transmission error which exceeds the error correction capability. A TS synthesizer section () in the internal reception unit () completely synchronizes a plurality of input transport streams by referencing synchronization bytes, PID, and CC values, and selects to output a TS packet having the error indicator flag not set to 1.

Digital data radio receiving device and method

In automated design, a useful insertion of a delay buffer or an increase in the delay time of the critical path could not been prevented. When inserting a logic element between two certain points on the circuit, substitution of other paths passing through the relevant insertion position is considered and the insertion position of the logic element is determined finally.

Method and apparatus for the design of a circuit

A parallel arithmetic-logical processing device in which arithmetic-logical processing is shared among and executed in a parallel fashion by a plurality of processing elements. The device includes a large-capacity serial access memory for continuous reading/writing of large-scale data, a small-capacity serial access memory for continuous reading/writing of small-scale data and a high-speed general-purpose random access memory for random writing/readout of small-scale data. A central processing unit (CPU) causes the memories to be used or not used depending on the scale of the arithmetic-logical processing. Since the serial access memory executes continuous data writing and reading, high-speed access may be achieved, so that it can be manufactured inexpensively with a large storage capacity. Consequently, the processing speed in the CPU may be increased, while the parallel arithmetic-logical processing device may be manufactured inexpensively.

Parallel arithmetic-logic processing device

A digital data transmitting apparatus comprises: an original block forming circuit for extracting image data in horizontal direction and/or vertical direction at intervals of a predetermined number of samples and forming an original block consisting of (n.times.n) pixel data; a differential block forming circuit for forming a differential block consisting of (m.times.m) pixel data with differential data between adjacent pixel data in horizontal and/or vertical direction and the pixel data concerned; a coding circuit for transform coding the original block and the differential block, respectively; a flag generation circuit for transmitting meaningful data of coefficient data generated by transform coding the differential block and generating a flag representing omission of the transmission of coefficient data where there is no meaningful data; and a transmission circuit for transmitting the flag and the pixel data of each of the block.

Digital data transmitting apparatus

A decoding method of Reed-Solomon code produces an error position polynomial .sigma.(x) and an error evaluation polynomial .omega.(x) by a Euclidean algorithm, whereby a syndrome polynomial S(x) is obtained, the highest degrees of the syndrome polynomial S(x) and of an initial polynomial x.sup.2t, which is determined by the number t of symbols to be corrected, are multiplied, while the degree is incrementally reduced, thereby obtaining polynomials h(x) and g(x) that satisfy the relation:

Method and apparatus for decoding Reed-Solomon code

An apparatus for encoding variable bit length data words into constant bit length data words concatenates the variable length data words supplied at a first data rate so as to output constant length data words at a second data rate. An apparatus for decoding constant bit length data words into variable bit length data words shifts and concatenates the constant bit length data words, determines when a variable length data word is present in the concatenated data, supplies information about the number of bits in the variable length data words which is used when shifting the next constant bit length data word, and outputs variable bit length data words.

Coding and decoding apparatus of variable length data

A highly efficient coding apparatus is configured to divide a digital picture signal into picture blocks and, based on a signal from a coding circuit for performing variable-length coding of each picture block, generate an output signal in the form of serial sync blocks. By inserting the most significant bit of a coded output signal for each picture element in a predetermined position of each sync block, a reproduced picture is obtained in a picture search mode in which a magnetic head scans a video tape across a plurality of tracks.

Highly efficient coding apparatus

A highly efficient coding apparatus for encoding digital video data in a block format and compressing the video data if required into a number of bits so that the total number of bits in the digital video data to be transmitted is less than that of a predetermined transmission capacity. Coefficient data having a DC component and a plurality of AC components for each block are generated by an orthogonal transformation. A distribution table of the AC coefficient data is generated during a predetermined period, and an accumulating distribution table is generated from the distribution table. The total bit number of the AC coefficient data generated during the predetermined period is controlled in response to the accumulating distribution table and the predetermined transmission capacity of the data transmission channel. The DC coefficient data, the controlled AC coefficient data and an additional code are transmitting for each of the predetermined periods.

An IC device has a first terminal for inputting date in the format for a four-line or two-line type bus line, and for outputting data, a second terminal for receiving a chip select signal, a third terminal for receiving a clock pulse, a fourth terminal for outputting data a first signal processor for receiving data from the first terminal in the format for a two-line type bus line and including an address signal and for outputting the data such first signal processor including a detector for detecting the address signal, a second signal processor for receiving the data supplied from the first terminal in the format of a four-line type bus line and outputting the data to the fourth terminal, the first and second signal processors being selectively enabled in accordance with the chip select signal, and a control unit for receiving the signal from the first or second signal processor and outputting the data to the first terminal or the first or second signal processors.

IC device compatible with input signals in the formats for two-line and

In an arithmetic circuit, a first input of m bits representing the vector expression of a first set of elements of a finite field GF(2m) is converted into the components of a matrix, and each component of the matrix is multiplied by second input of m bits representing the vector expression of a second set of elements of the finite field. A vector product of the first and second inputs is thereby obtained.

Arithmetic circuit for obtaining the vector product of two vectors

There is provided a digital time base corrector in which a digital input signal of one block consisting of a continuous data time sequence is converted to a digital signal including data lack intervals or vice versa by a variable delay circuit. A signal selecting circuit is divided into N first unit selecting circuits and a second unit selecting circuit. M of the output signals of a shift register are inputted to the first unit selecting circuits, by which one of them is selected. The outputs of the N first unit selecting circuits are supplied to the second unit selecting circuit, by which one of them is selected. A pipeline process is performed by inserting a delay circuit to delay the signal for the time of one clock period into the input/output line of the second unit selecting circuit. Further, the selecting signal can be made variable for every one clock and a delay circuit is inserted on the output side of a selecting signal forming circuit. With this corrector, the influence of the gate delay of the selectors can be reduced and the high speed data process can be performed.

Digital time base corrector

A method and apparatus are provided for encoding successive n-bit information words into successive m-bit code words wherein m&gt;n. Each n-bit information word is assigned with a respective set of m-bit code words. Each set of code words is comprised of either two or four words. The words in each two-word set have zero disparity, and their first bits are of opposite logical sets. In the four-word sets, two words have positive disparity and their first bits are of opposite logical sense, and the other two words have negative disparity and their first bits also are of opposite logical sense. The particular m-bit code word that is selected from the set associated with the n-bit word commences with the same bit as the last bit of the immeditely preceding code word, and the selected code word exhibits a disparity that, when combined with the digital sum variation of the preceding encoded code words, reduces the overall digital sum variation toward zero.

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Kanagawa, Japan

Norihisa Shirota