Kabushiki Kaisha Toshiba

Kabushiki Kaisha Tosbhia

Norihisa Arai

Riichiro Shirota

Seiichi Aritome

Kazuhiro Shimizu

Tsutomu Takahashi

Hiroyuki Kanaya

Hiroaki Hazama

Akira Goda

Hiroyuki Takenaka

Akira Shimizu

Tomio Katata

Hirohisa Iizuka

Hiroshi Mochizuki

Osamu Hidaka

Kumi Okuwada

Naoki Koido

Tohru Maruyama

Kazuo Hatakeyama

Tomoko Yamane

Sumito Ootsuki

Tomoaki Hatano

Fumitaka Arai

Shigeru Atsumi

Yuji Takeuchi

Toshitake Yaegashi

Hiroyuki Kutsukake

Akira Umezawa

Hironori Banba

Koki Ueno

Takeshi Nakano

Toshifumi Minami

Minori Kajimoto

Keisuke Murayama

Yoshiko Kato

Kenji Gomikawa

Takeshi Shimane

Eiji Kamiya

Masayuki Akou

Kazunori Masuda

Atsuhiro Suzuki

Masao Tanimoto

Ryo Sudo

Norio Magome

Kazuki Uchino

Chiaki Hoshino

Hiroshi Shimode

According to one embodiment, a semiconductor device includes: a semiconductor layer of a first conductivity type, and the semiconductor layer having a first and a second surfaces; a first conductive layer penetrating from the first surface side to the second surface side of the semiconductor layer; a first semiconductor region of a first conductivity type surrounding part of the first conductive layer on the second surface side of the semiconductor layer, a portion other than a front surface of the first semiconductor region being surrounded by the semiconductor layer; and a first insulating film provided between the first conductive layer and the semiconductor layer and between the first conductive layer and the first semiconductor region, a concentration of an impurity element contained in the first semiconductor region being higher than a concentration of an impurity element contained in the semiconductor layer.

Semiconductor device

According to one embodiment, a semiconductor device includes: a semiconductor substrate, the semiconductor substrate having first and second surfaces; conductive regions extending in a direction from the first surface side toward the second surface side of the semiconductor substrate, the conductive regions including first and second vias; a first semiconductor region surrounding a part of each of the conductive regions on the second surface side of the semiconductor substrate, a portion other than a front surface of the first semiconductor region being surrounded by the semiconductor substrate; a first electrode provided on the second surface side; second electrodes provided on the first surface side, one of the second electrodes being in contact with one of the conductive regions; and an insulating film provided between each of the conductive regions and the semiconductor substrate, and between each of the conductive regions and the first semiconductor region.

According to one embodiment, a semiconductor device includes: a semiconductor layer of a first conductivity type, the semiconductor layer having a first surface and a second surface on an opposite side to the first surface; a plurality of conductive layers extending in a direction from the first surface side toward the second surface side of the semiconductor layer; a first semiconductor region of a second conductivity type surrounding part of each of the plurality of conductive layers on the second surface side of the semiconductor layer, a portion other than a front surface of the first semiconductor region being surrounded by the semiconductor layer; and an insulating film provided between each of the plurality of conductive layers and the semiconductor layer and between each of the plurality of conductive layers and the first semiconductor region.

A semiconductor device includes a semiconductor substrate, an element isolation insulating film dividing an upper portion of the substrate into a plurality of first active regions, a source layer and a drain layer, a gate electrode, a gate insulating film, a first punch-through stopper layer, and a second punch-through stopper layer. The source layer and the drain layer are formed in spaced to each other in an upper portion of each of the first active regions. The first punch-through stopper layer is formed in a region of the first active region directly below the source layer and the second punch-through stopper layer is formed in a region of the first active region directly below the drain layer. The first punch-through stopper layer and the second punch-through stopper layer each has an effective impurity concentration higher than the semiconductor substrate. The first punch-through stopper layer and the source layer are separated in the channel region. The second punch-through stopper layer and the drain layer are separated in the channel region.

Semiconductor device and method for manufacturing the same

According to an aspect of the present invention, there is provided a semiconductor device including: a semiconductor substrate; active areas with island-like shapes formed on the semiconductor substrate; an element isolation area surrounding the active areas and including an element isolation groove formed on the semiconductor substrate and an element isolation film embedded into the element isolation groove; gate insulating films each formed on corresponding one of the active areas and having a first end portion that overhangs from the corresponding active area onto the element isolation area at one side and a second end portion that overhangs from the corresponding active area onto the element isolation area at the other side, wherein an overhang of the first end portion has a different length from a length of an overhang of the second end portion.

Semiconductor device and manufacturing method thereof

A semiconductor device has a semiconductor substrate of a first conductivity type; first to third high-voltage insulated-gate field effect transistors formed on a principal surface of the semiconductor substrate; a first device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the second high-voltage insulated-gate field effect transistor from each other; a second device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the third high-voltage insulated-gate field effect transistor from each other; a first impurity diffusion layer of the first conductivity type that is formed below the first device isolation insulating film; and a second impurity diffusion layer of the first conductivity type that is formed below the second device isolation insulating film.

A semiconductor memory device includes a memory cell array which includes at least one memory unit having a preset number of memory cell transistors and a selection gate transistor on a source side, a preset number of word lines respectively connected to control gates of the preset number of memory cell transistors, and a selection gate line on a source side connected to a gate electrode of the selection gate transistor on the source side. In the semiconductor memory device, a distance C between the selection gate line at least on the source side and one of the word lines adjacent thereto is set to n*A+(n&#x2212;1)B, where n is an integer greater than or equal to 2, A indicates the pitch between adjacent ones of the preset number of word lines, and B indicates the width of each of the preset number of word lines.

Semiconductor memory device having plural word lines arranged at narrow pitch and manufacturing method thereof

A trench isolation region is formed in a surface region of a semiconductor substrate to form a MOS type element region. A mask layer having an opening portion is formed on the semiconductor layer, the opening portion continuously ranging on the entire surface of the MOS type element region and on part of the trench isolation region provided around the MOS type element region. A first impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated in the semiconductor layer under the bottom surface of the shallow trench isolation region. A second impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated on the midway of the depth direction of the trench isolation region. Then, the first and second impurity ions are activated.

Semiconductor device having isolation region and method of manufacturing the same

A gate oxide film and a first layer of a multilayered gate electrode are stacked on a substrate and by a gate prefabrication technique, an oxide layer of an element isolation region is formed in a self-alignment manner using the first layer of the gate electrode as a mask, impurities for a transistor channel control are doped by ion implantation via the first layer of the gate electrode and the gate oxide film, and the doped impurities are activated by a heating step, whereby an impurity profile at the transistor channel portion is precisely formed.

Semiconductor device including impurities in substrate via MOS transistor gate electrode and gate insulation film

A first well of the same conductivity type as that of a semiconductor substrate and a second well of a conductivity type opposite to that of the semiconductor substrate, are formed in the semiconductor substrate. The second well isolates the semiconductor substrate and the first well from each other. Phosphorus ions for forming the bottom of the second well are implanted into the semiconductor substrate more deeply than boron ions for forming the first well. The depths to which these ions are implanted can be varied by acceleration energy of the ions. If the ions are so implanted, the total sum of impurities constituting the second well can be decreased within the surface area of the first well.

Semiconductor device having a double-well structure and method for manufacturing the same

A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.

Semiconductor device having serially connected memory cell transistors provided between two current terminals

The semiconductor device is constituted in such a manner that a switching transistor having a drain region and a source region which are comprised of an impurity-diffused region is formed in the surface layer portion of a semiconductor substrate. On the semiconductor substrate containing the transistor, a first insulation film is formed, and, at the upper layer side of the first insulation film, a capacitor is formed. The capacitor is comprised of a lower electrode, an inter-electrode insulation film comprising one of ferroelectric and high-permittivity dielectric, and an upper electrode. Before the inter-electrode insulation film is formed, a second insulation film is formed so as to cover the side face portion of the inter-electrode insulation film, the second insulation film protecting the side face portion of the inter-electrode insulation film. One of the drain region and the source region and one of the upper electrode and the lower electrode of the capacitor are connected to each other by an electrode wiring. A wiring connected to the other one of the drain region and the source region is formed on the semiconductor substrate.

Semiconductor device and method for the manufacture thereof

A method of fabricating a semiconductor device which has a cell array with non-volatile memory transistors and a peripheral circuit including a first transistor and a second transistor as driven by a lower voltage than the first transistor is disclosed. The method includes the steps of forming over a semiconductor substrate a first gate dielectric film for use in the first transistor, selectively etching the first gate dielectric film in the cell array region to expose the substrate, forming over the exposed substrate a second gate dielectric film which is for use as a tunnel dielectric film of the memory transistors, forming a first gate electrode material film over the first and second gate dielectric films, selectively etching the first gate electrode material film and its underlying first gate dielectric film in the second transistor region, forming over the exposed substrate a third gate dielectric film which is for use in the second transistor, forming a second gate electrode material film over the third gate dielectric film, and forming gates of the respective transistors while letting the gates at least partly include the first and second gate electrode material films.

Semiconductor device and method of fabricating the same

A gate oxide film and a first layer of a multi-layered gate electrode are stacked on a substrate and by a gate prefabrication technique, an oxide layer of an element isolation region is formed in a self-alignment manner using the first layer of the gate electrode as a mask, impurities for a transistor channel control are doped by ion implantation via the first layer of the gate electrode and the gate oxide film, and the doped impurities are activated by a heating step, whereby an impurity profile at the transistor channel portion is precisely formed.

Method of manufacturing semiconductor device including process for implanting impurities into substrate via MOS transistor gate electrode and gate insulation film

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Omiya, Japan

Norihisa Arai