Sony Corporation

Sanyo Electric Co., Ltd.

Sony Semiconductor Solutions Corporation

Norihiro Nikai

Atsushi Suzuki

Takashi Shoji

Hayato Wakabayashi

Naoki Kawazu

Takumi Oka

Nobutaka Shimamura

Yuuki Yamagata

Toshiki Kainuma

Masashi Akamatsu

Tohru Kikawada

Atsushi Wada

Kuniyuki Tani

Seiichi Banba

Yuusuke Nishida

Yasuyuki Kimura

Hayato Gouji

Isamu Izumimoto

Kenichi Kato

The present technology relates to an image pickup element, a control method, and an image pickup device which realize easier and more diversified data output. In one aspect of the present technology, a plurality of signal lines for transmitting a pixel signal read from a pixel is allocated to each column, and different reading modes of the pixel signals are respectively allocated to the signal lines of each column. Regarding each column of the pixel array connected to the pixel corresponding to the mode, the pixel signal is read from the pixel connected to the signal line corresponding to the reading mode of the pixel signal in the mode, and the read pixel signal is transmitted via the signal line. The present technology is applied to, for example, an image pickup element and an image pickup device.

Image pickup element, control method, and image pickup device

The present technique relates to an imaging element, a driving method of the imaging element, and an electronic device that can improve image quality of an image in a case where two or more read scans of pixel signals are performed in parallel. The imaging element includes a pixel area including a plurality of pixels arranged in a matrix, a vertical drive circuit that drives the pixels in the pixel area row-by-row, and a column signal processing circuit that can read pixel signals of a plurality of rows in the pixel area in one horizontal period. The vertical drive circuit performs two or more read scans of the pixel signals in the pixel area in parallel and controls a timing of moving a read row of each read scan by equal to or more than a predetermined amount of movement on the basis of a position of a read row of another read scan. The present technique can be applied to, for example, a CMOS image sensor.

Imaging element, driving method of imaging element, and electronic device

To reduce influence occurring between signals simultaneously outputted from two pixels of the same pixel column via mutually different signal lines as much as possible. A solid-state imaging element including: a pixel column in which a plurality of pixels are juxtaposed in a column form; three or more juxtaposed signal lines each used for an output of a pixel included in the pixel column; and an A/D conversion section configured to convert an analog voltage outputted by the pixel to the signal line to a digital value. For a first pixel and a second pixel included in the pixel column, signal lines of connection destinations of these pixels are different from each other, and timings of outputs of analog voltages of these pixels to the signal lines coincide, an output from the first pixel to the signal line is permitted and an output from the second pixel to the signal line is disabled in a case where a prescribed number of one or more of signal lines or shield lines do not exist between the signal line that is a connection destination of the first pixel and the signal line that is a connection destination of the second pixel, and both outputs from the first pixel and the second pixel to the signal lines are permitted in a case where the prescribed number or more of signal lines or shield lines exist between the signal line that is a connection destination of the first pixel and the signal line that is a connection destination of the second pixel.

Solid-state imaging element and method for controlling solid-state imaging element

A solid-state imaging device includes: a pixel array section having an effective pixel region formed by a plurality of pixels which are disposed in the form of a matrix, each of which includes a photoelectric conversion device and a transistor reading out an electric charge obtained by photoelectric conversion at the photoelectric conversion device, and which are illuminated by light and a light-shielded pixel region formed by a plurality of pixels which are shielded from light; a row scan section selecting and controlling each row of pixels of the pixel array section to output a signal from each of the pixels of the selected row of pixels to a column signal line provided in association with the row of pixels; and an A-D conversion section converting the signal output from the signal line into a digital signal.

Solid-state imaging device and imaging apparatus

A solid-state imaging device includes: a pixel unit in which a plurality of photoelectric conversion elements are arranged; a comparison unit comparing a reference signal with a signal acquired by the photoelectric conversion element of the pixel unit; a reference signal generating unit generating the reference signal; a counting unit counting an amount of time when the relative magnitude of the pixel signal and the reference signal is inverted by the comparison unit; and an offset setting unit setting an offset in the reference signal generated by the reference signal generating unit.

Solid-state imaging device, method of driving solid-state imaging device, and imaging apparatus

In an analog-to-digital converter circuit of pipeline type configured by cascade-connecting a plurality of analog-to-digital conversion blocks, at least analog-to-digital conversion blocks at an initial stage excluding an analog-to-digital conversion block at a final stage have each a function as an amplifier and are switched by a control signal inputted externally so that the analog-to-digital conversion blocks each operates as the amplifier. When the analog-to-digital conversion blocks each having the function as the amplifier are each operated as the amplifier by the control signal, a digital signal is generated by using data outputted from an analog-to-digital conversion block provided subsequent to the analog-to-digital conversion blocks operating as the amplifiers.

Analog-to-digital converter circuit and signal processing circuit

The collectors of transistors are connected via respective resistances to a power supply terminal receiving a power supply voltage. The emitters of the transistors are connected to a ground terminal via respective resistances. A shunt resistance, a FET, and a shunt resistance are connected in series between nodes connected to the respective emitters of the transistors. The gate of the FET is connected via a resistance to a control terminal receiving a control voltage. The shunt resistances and FET form a variable resistance circuit.

Variable impedance circuit, variable gain differential amplifier, multiplier, high-frequency circuit and differential distributed amplifier

In an analog-to-digital conversion circuit, the gain of an operational amplification circuit in each of first- to third-stage circuits is two. The reference voltage range of a sub-A/D converter in each of the stages of circuits is set to one-half the reference voltage range of a D/A converter, so that the output voltage range of the D/A converter coincides with the output voltage range of the operational amplification circuit. When the voltage range of the analog input signal is VIN , the full-scale range of the sub-A/D converter is switched to VIN , and the gain of the operational amplification circuit is one. When the voltage range of the analog input signal is VIN /2, the full-scale range of the sub-A/D converter is switched to VIN /2, and the gain of the operational amplification circuit is two.

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Fukuoka, Japan

Norihiro Nikai