Sony Corporation

Sony Semiconductor Solutions Corporation

Norihiro Murayama

Kosuke Fujita

Kenji Komori

Atsushi Hirabayashi

Toshikazu Yoshida

Tomonori Nakajima

Toshihisa Hyakudai

Kohei Yamamoto

Mitsuru Ikeda

Hiroshige Takakuwa

Kazuya Nakamura

Takahiro Ando

Masatomo Miyashita

Disclosed is a tuner device including an input terminal, a separator, a first amplifier, a second amplifier, and a tuner. The input terminal receives an input of a reception signal of satellite digital broadcasts. The separator is connected to the input terminal and adapted to frequency-separate a first signal and a second signal. The first signal is in a low-frequency domain of the reception signal, and the second signal is in a high-frequency domain of the reception signal. The first and second amplifiers respectively amplify the first and second signals. The tuner receives an input of output signals from the first and second amplifiers.

Tuner device

There is provided a reception device including first and second reception circuits configured to receive transmission signals, a first oscillation circuit configured to generate a differential signal having a predetermined frequency on the basis of an oscillation signal acquired from a connected crystal oscillator, and to supply the generated differential signal to the first reception circuit as a reference frequency signal, and a second oscillation circuit configured to be supplied with an oscillation signal having one of phases in the differential signal acquired by the first oscillation circuit, to generate a differential signal having a predetermined frequency on the basis of the supplied oscillation signal, and to supply the generated differential signal to the second reception circuit as a reference frequency signal.

Reception device and electronic apparatus

An electronic apparatus is provided and includes a first IC having an internal configuration section, a nonvolatile memory, and an interface section. The electronic apparatus also includes a second IC having a signal processing section, and a correction-data supplying section.

Electronic apparatus, electronic-apparatus adjustment method and integrated circuit

Phase locked loop (PLL) detection circuit that can improve the stability of operation, avoid occurrence of an erroneous operation, and perform PLL lock judgment correctly. Whether a PLL circuit that consists of a phase comparator, a low-pass filter, and a VCO is in a lock state is judged based on a phase error signal in the PLL circuit. The level of the phase error signal is compared with two threshold values, VRL and VRH. When the phase error signal is somewhere between VRL and VRH, a judgment is made that the PLL circuit is in a lock state. A judgment that the PLL circuit is out of a lock state is made in the other cases. This makes it possible to output a correct and stable PLL lock judgment signal.

PLL detection circuit with lock judgement circuit

A high impedance circuit capable of operating at a low voltage without narrowing the dynamic range is provided, which includes a first and a second transistors forming differential-pair type circuit, a third and fourth transistors, a pair of collector resistance elements, a resistance element and a pair of current source circuits. The third and the fourth transistors serve as emitter follower circuits which also functions as a DC shift with respect to the differential-pair type circuit, as well as buffer circuits for heightening an input impedance of the first and the second transistors looked from the base side of the third and the fourth transistors. The current flowing in the resistance element is made current-fedback with respect to the resistance elements by the third and the fourth transistors. The input impedance is determined as Z,&equals;V,/ i,&equals;(R,&times;R,)/(R,&minus;R,), and when R,&equals;R,, the high impedance circuit becomes infinite impedance.

High impedance circuit

A high impedance circuit capable of operating at a low voltage without narrowing the dynamic range is provided, which includes a first and a second transistors forming differential-pair type circuit, a third and fourth transistors, a pair of collector resistance elements, a resistance element and a pair of current source circuits. The third and the fourth transistors serve as emitter follower circuits which also functions as a DC shift with respect to the differential-pair type circuit, as well as buffer circuits for heightening an input impedance of the first and the second transistors looked from the base side of the third and the fourth transistors. The current flowing in the resistance element is made current-fedback with respect to the resistance elements by the third and the fourth transistors. The input impedance is determined as Z1=V1/i3=(R1.times.R2)/(R1-R2), and when R1=R2, the high impedance circuit becomes infinite impedance.

An impedance conversion circuit for the use with a video apparatus, an audio apparatus, or a communication apparatus is provided. The impedance conversion circuit can be used at a frequency higher than that conventionally used and is suitable for formation as an integrated circuit. A video apparatus using this impedance conversion circuit, and the like are also proposed. Driving current is supplied to first and second terminals of an impedance circuit in accordance with voltages of first and second input terminals, respectively, and current is made to flow out of the second and first output terminals in accordance with the first and second terminal voltages of the impedance circuit, respectively.

Impedance conversion circuit, video apparatus, audio apparatus, and

An amplifier circuit in which a differential pair of transistors (1a), (1b) is provided. An impedance (2) of a value 2.Z.sub.e is connected in series between the emitters of the transistors (1a), (1b) and these emitters are grounded by way of current sources (3a), (3b) respectively. Input signal sources (4a), (4b) of voltage values.+-.V.sub.IN are connected to the bases of the transistors (1a), (1b) by way of the base-emitter paths of the transistors (5a), (5b) which form a buffer circuit (10). The emitters of the transistors (5a), (5b) are in turn grounded by way of current sources (6a), (6b) respectively. Further, the collectors of each of the transistors (1a), (1b) are connected to the base of the other transistors by way of the base-emitter paths of the transistors (5a), (5b) respectively.

Negative amplifier circuit

A two-terminal paired circuit is disclosed which comprises two sets of differential pairs wherein a first set of the differential pair includes two transistors collectors of which are connected to a pair of input terminals and to a bias circuit serving also as a DC shift, bases of which are connected to the bias circuit to apply a voltage feedback from the collectors to the bases and emitters of which are connected to a constant current source and have an impedance element connected therebetween, a second set of the differential pair includes two transistors collectors of which are connected to a pair of output terminals and to a bias circuit serving also as a DC shift, bases of which are connected to the bias circuit to apply a voltage feedback from the collectors to the bases and emitters of which are connected to a constant current source and have an impedance element connected therebetween, and the voltage feedbacks together with the two sets of differential pairs are applied symmetrical with respect to left and right, whereby the impedances connected between the emitters exist in series between the input and output terminals.

Growing community of inventors

Chiba, Japan

Norihiro Murayama