Fujitsu Corporation

Fujitsu Microelectronics Limited

Norihiro Ikeda

Koichi Kuroiwa

Shoji Taniguchi

Masami Kanasugi

Kazuhisa Obuchi

Shunji Miyazaki

Makoto Muranushi

A receiving device in a communication system that separates one frame of information bits into plural blocks, performs turbo encoding of the information bits of each block and transmits the result, and decodes the encoded information bits, where the receiving device includes plural decoders number of which is less than the number of blocks per frame. Each decoder performs a decoding process on encoded information bits of each block that have been expressed by likelihood, when a condition for stopping decoding is met, executes the decoding process of encoded information bits of another block for which decoding has not yet been performed. When the condition for stopping decoding has been met for all blocks before the number of times decoding has been performed for each decoder reaches a preset maximum number of repetitions, the decoding results of all the blocks are serially combined, an error detection process is executed.

Receiving device and decoding method thereof

A turbo decoding apparatus comprises: a backward-probability calculation unit that executes backward-probability calculation from time N to time 0 with respect to coded data having an information length N (N is a natural number) which is encoded with turbo-encoding; a storage unit to store backward-probability calculation results extracted from a plurality of continuous backward-probability calculation results regarding a predetermined section of at intervals of n-time; a forward-probability calculation unit that executes forward-probability calculation from time 0 to time N with respect to the coded data; and a decoded result calculation unit that calculates a decoded result of the coded data through joint-probability calculation using forward-probability calculation results by the forward-probability calculation unit and the backward-probability calculation results stored in the storage unit and backward-probability calculation results obtained through recalculation by the backward-probability calculation unit.

Turbo decoding apparatus

A semiconductor having an internal memory of the present invention comprises a first memory copying and holding a data held in a storage device; a second memory holding a check code of the data held in the first memory, and being constantly supplied with a source voltage not lower than a data-holding-guarantee voltage; a data check unit detecting error in the data held by the first memory based on the check code; and reloading units copying only the data corresponded to the block having a data error detected therein by the data check unit, from the storage device to the first memory, to make it possible to detect any error in the data held in the first memory to thereby guarantee the data, and to lower the source voltage to be supplied to the first memory.

Semiconductor device

A processor () having an instruction memory () supplies addressing information and setting values to be set to registers (REGA to REGD) to a setting interface unit (), and address values of the registers are outputted from an address output unit () based on the addressing information. The outputted address values and the setting values are outputted respectively to registers to set setting values, so that the processor can set the setting values to be set to the registers without being conscious of the addresses of the registers, and thus it becomes possible to reduce addressing portions of the respective registers in the instruction codes, and reduce the number of instruction codes, which facilitates coding of the instruction codes.

Initializing function block registers using value supplying setting interface coupled to table linking block identifier to multiple register address set

In a code generation device for generating a code: a binary-data generation circuit generates first binary data items indicating every (m&plus;1)th one of n successive binary numbers, where m&gE;1 and n&gE;2. A binary-data derivation circuit derives m&plus;1 second binary data items indicating m&plus;1 binary numbers from each of the first binary data items, where the m&plus;1 binary numbers include the first binary data item. A first processing circuit performs a predetermined common operation on identical portions of the m&plus;1 second binary data items, and a second processing circuit performs individually predetermined operations on non-identical portions of the m&plus;1 second binary data items, where states of corresponding bits in the non-identical portions of the m&plus;1 second binary data items are not identical. A combining circuit combines the outputs of the first and second processing circuits.

Growing community of inventors

Kawasaki, Japan

Norihiro Ikeda