Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Nuvoton Technology Corporation Japan

Panasonic Intellectual Property Management Co., Ltd.

Panasonic Semiconductor Solutions Co., Ltd.

Norihiko Sumitani

Hidenari Kanehara

Kazuki Tsujimura

Akira Masuo

Shigeo Houmura

Yosuke Higashi

Yutaka Abe

Hiroshi Fujinaka

Kazuko Nishimura

Masaya Sumita

Satoshi Ishikura

Yasuhiro Agata

Tsuyoshi Koike

Takayasu Kito

Takayuki Nishitani

Toshio Terano

Youji Nakai

A solid-state imaging device includes: a plurality of pixel circuits arranged in rows and columns; a plurality of selector circuits that each receive, as inputs, two pixel signals corresponding to two columns different from each other; k column AD conversion circuits that perform AD conversion on pixel signals output from the plurality of selector circuits, k being an integer greater than or equal to two; and m column AD conversion circuits that are provided redundantly. In the solid-state imaging device, the plurality of selector circuits selectively exclude, from among the k column AD conversion circuits and the m column AD conversion circuits, m column AD conversion circuits corresponding to m columns adjacent to each other, and associate k pixel signals output from the plurality of pixel circuits with k column AD conversion circuits which have not been excluded.

Solid-state imaging device with redundant ad conversion circuits and selective exclusion

A solid-state imaging device includes: a latch circuit that holds a digital signal of pixel data, the digital signal having 1 bit; a driver circuit that outputs the digital signal held in the latch circuit to a read bit line pair; a sense amplifier connected to the read bit line pair; and a selector circuit that selects whether the digital signal output from the sense amplifier is to be output in normal form or in inverted form.

Solid-state imaging device

A solid-state imaging device includes a first converter which converts an analog signal representing a pixel value to an upper bit of a digital signal, and a second converter which converts the analog signal to a lower bit of the digital signal. The second converter includes a first latch circuit which latches, as phase information, a plurality of clock signals having different phases upon conversion to the upper bit in the first converter, a conversion circuit which generates the lower bit of the digital signal by converting the phase information to a binary value, and an adder, and a second latch circuit which latches an addition result of the adder. The adder adds the binary value converted by the conversion circuit and a value latched by the second latch circuit.

Solid-state imaging device and imaging system

A solid-state imaging device includes a first A/D converter circuit and a second A/D converter circuit per column. The first A/D converter circuit performs a first A/D conversion that (i) refines, using a first comparator, a range including a potential of an analog signal through a binary search, and (ii) generates, based on a result of the binary search, a first digital signal being a high-order portion of the digital signal. The second A/D converter circuit performs a second A/D conversion that generates a second digital signal being a low-order portion that is a remainder of the digital signal by measuring a time required for an output of the second comparator to be inverted, the second comparator comparing a quantitative relationship between the analog signal refined and a ramp signal.

Solid-state imaging device, and camera system using same

An imaging device includes: a pixel that outputs a pixel signal corresponding to incident light; a comparator that compares the pixel signal with a reference signal and generates an output signal that indicates a comparison result; a counter that generates a digital signal corresponding to the pixel signal by counting the number of periods until the output signal is inverted, the counter including first to fourth counter parts, each of which corresponds to one of bits included in the digital signal; a memory that stores the digital signal, the memory including first to fourth memory parts corresponding to the first to fourth counter parts; and first and second lines. The first and third counter parts are respectively connected to the first and third memory parts through the first line. The second and fourth counter parts are respectively connected to the second and fourth memory parts through the second line.

Imaging device and camera system

A solid-state imaging device includes a plurality of pixels arrayed in a matrix, a plurality of first latch circuits, a first read bit line, a plurality of first driver circuits, a first amplifier, a second latch circuit, a second driver circuit, and a column scanning circuit. Each of the plurality of first latch circuits holds first pixel data which is obtained from a pixel located on the corresponding unit column. Each of the plurality of first driver circuits outputs the first pixel data, which is held in a corresponding one of the first latch circuits, to the first read bit line. The first amplifier amplifies a voltage of the first read bit line to generate first data. The second latch circuit holds the first data. The column scanning circuit sequentially outputs a plurality of the first pixel data by sequentially selecting the plurality of first driver circuits and selecting the second driver circuit. The second driver circuit outputs the first data to a read bit line different from the first read bit line.

A semiconductor memory includes a plurality of memory cells. The plurality of memory cells each include a latch having two inverters, where an input node and an output node of one of the inverters are respectively coupled to an output node and to an input node of the other one of the inverters, a first switch coupled in series with the latch between a first and a second power sources, and a second switch coupled in parallel with the first switch.

Semiconductor memory

A memory macro includes: a plurality of memory cells arranged in a matrix; a plurality of word lines corresponding to rows of the plurality of memory cells; and a plurality of word line drivers configured to drive the plurality of word lines. The voltage of the word lines in their activated state is set to vary with threshold voltage characteristics of a p-channel transistor and an n-channel transistor.

Semiconductor integrated circuit

A dummy cell array is provided in a memory cell array, and an intermediate buffer is provided between input/output circuits, whereby control signals to the input/output circuits can be operated at high speed and with a high frequency while the area increasing effect is reduced even in a memory with a large bit width.

Semiconductor memory device

A semiconductor memory device includes: static memory cells arranged in a matrix; a read bit line for transmitting data read from one of the memory cells; a write bit line for transmitting data to be written to one of the memory cells; an input data line for transmitting data which is received from outside and is to be written in one of the memory cells; and a selector for selectively transmitting data of the read line or the input data line to the write bit line.

Semiconductor memory device including write selectors

In a memory cell having a first and a second load transistor, a first and a second drive transistor, and a first and a second access transistor, a third access transistor provided between a first bit line and a first memory node and having a gate terminal connected to a first column line and a fourth access transistor provided between a second bit line and a second memory node and having a gate terminal connected to a second column line, are additionally provided.

The decoder circuit includes: a power supply control circuit for supplying a first voltage; first and second transistors connected in series between the power supply control circuit and a first reference node; and third and fourth transistors connected between a connection node between the first and second transistors and a second reference node. The first transistor receives a first signal at its gate, and the second transistor receives a second signal corresponding to the first signal at its gate. The third transistor receives a third signal at its gate, and the fourth transistor receives a fourth signal corresponding to the third signal at its gate. The potential difference between the first voltage and the first reference node is smaller than the potential difference between the first reference node and the second reference node.

Decoder circuit

A semiconductor memory includes: first and second bit lines; a precharge circuit for precharging the first and second bit lines to a predetermined potential; a plurality of memory cells each connected to the first or second bit line, a selected one of the memory cells maintaining or discharging one of the precharged first and second bit lines according to a signal held by the selected memory cell; word lines for selecting the memory cells; first and second reference cells connected to the first and second bit lines, respectively, a selected one of the first and second reference cells discharging the first or second bit line connected to the selected reference cell; and first and second reference cell word lines for selecting the first and second reference cells, respectively.

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Osaka, Japan

Norihiko Sumitani