Oki Electric Industry Co., Ltd.

Oki Semiconductor Co., Ltd.

Lapis Semiconductor Co., Ltd.

Norihiko Satani

Tetsuya Mitoma

Yuichi Matsushita

Shizuo Cho

Masakuni Kawagoe

Takahiro Imayoshi

Yoshihiro Nakatake

Akihiro Narumi

Shinichiro Sato

A drive device drives a display panel through alternately applying a positive polarity gradation voltage and a negative polarity gradation voltage to the display panel. The drive device includes an amplifier unit for amplifying a voltage applied to an input to obtain an amplified gradation voltage, and a voltage generation unit for generating the positive polarity gradation voltage and the negative polarity gradation voltage according to the amplified gradation voltage. The amplifier unit selects one of the positive polarity gradation voltage and the negative polarity gradation voltage immediately before the amplifier unit switches a gradation reference voltage. The selected gradation voltage has a polarity the same as that of the gradation reference voltage to be applied to the input line after the amplifier unit switches the gradation reference voltage.

Drive device having amplifier unit for applying gradation reference voltage

In a semiconductor circuit, a high frequency level detecting unit detects a level of a high frequency component adjusted with a first adjusting unit, and a first control unit controls a first gain of the adjusting unit according to the level of the high frequency component thus detected. Further, a low frequency level detecting unit detects a level of a low frequency component adjusted with a second adjusting unit. A second control unit controls a second gain according to the level of the high frequency component and the level of the low frequency component thus adjusted, so that a difference between the level of the high frequency component adjusted with the first adjusting unit and the level of the low frequency component adjusted with the second adjusting unit becomes smaller than a specific level determined in advance.

Semiconductor circuit and method of retrieving signal to semiconductor circuit

The present invention provides an arbitration circuit capable of stable operation regardless of timings for read and write requests. A latch signal of a predetermined pulse width is generated in accordance with a read request signal or a write request signal and supplied to latches. Flip-flops or FFs respectively fetch therein write and read requests produced within the time of the latch signal. The latches respectively output the fetched requests as signals at the same timing. Thus, since the timings for the signals coincide with each other even when the write request and the read request are made at close intervals while the latch signal is being outputted from a latch controller, a write control signal or a read control signal can be stably outputted in accordance with the order of priority defined in advance by a delay unit.

Abitration circuit providing stable operation regardless of timing for read and write requests

A semiconductor memory device includes a redundant memory cell, an electrode and an output circuit. The redundant memory cell is used instead of a memory cell when the memory cell has a defect. The electrode applys with a test signal for setting a test condition from outside in testing the redundant memory cell. The output circuit outputs data read out of the memory cell and the redundant memory cell. When the test signal is applied to the electrode to set the test condition for the redundant memory cell, the output circuit is configured to output data read out of the redundant memory cell at a level different from a signal level of data readout of the memory cell for output.

Semiconductor memory device

Switching is provided such that the bit lines between a sense amp and the memory cells connected to the sense amp are put into a non-conducting state during normal operation, and are put into a conducting state during characteristic tests. A control circuit is provided which outputs control signals to control the conducting state of this switching. The control circuit has a signal generation unit and a control signal switching unit. The signal generation unit generates driving signals and the inverted signals of these driving signals in order to drive the control circuit using applied voltages from outside. The control signal switching unit includes a plurality of transmission gates, and outputs control signals according to memory cell select signals and the inverted signals of same, based on the combination of conducting and non-conducting states of the transmission gates, which depend on the supply of driving signals and inverted driving signals.

Semiconductor storage device

A new and improved semiconductor memory that facilitates machining of iterated circuits and solves the problems of the prior art such as the lengthy machining process, the compromised machining accuracy and the considerable time required for device evaluation is provided. A semiconductor memory is provided with a plurality of output circuits and a fuse circuit connected to each of the output circuits. The fuse circuit outputs output signals N and N to the individual output circuits, the signal levels of which are fixed to either H level or L level depending upon whether or not fuses f and f in the fuse circuit are disconnected. The output circuits are each provided with an output buffer circuit unit and a pre-driver circuit unit that drives the output buffer circuit unit. The driving capability of the pre-driver circuit unit is determined by the output signal from the fuse circuit. By providing the fuses that can be easily disconnected with a laser beam, it becomes possible to adjacent the gate widths of the pre-drivers at the plurality of output circuit units all at once. As a result, the length of machining time can be reduced compared to that required in the prior art technology.

Semiconductor memory that enables dimensional adjustment by using a fuse

The present invention provides a semiconductor integrated circuit that solves the aforementioned problems. A semiconductor integrated circuit of the present invention has a plurality of memory cells, for respectively storing data, bit line pairs supplied with data read from the memory cells and sense amplifiers for amplifying data supplied to the bit line pairs. The integrated circuit also has first and second data bus driving transistors, and a pair of data buses. The first data bus driver transistors each have a control terminal, for receiving data supplied to one bit line of the bit line pairs, a second terminal connected to a common node, and a third terminal, while the second data bus driver transistors each have a control terminal, for receiving data supplied to the other bit line of the bit line pairs, one terminal connected to the common node, and a third terminal. The integrated circuit of the present further has a transfer circuit, connected between the pair of data buses and the third terminals of the first and second data bus driver transistors, for electrically connecting the third terminals to the pair of data buses in response to a row select signal, and an output control circuit, connected to a first power supply potential node supplied with a first power supply potential, a second power supply potential node supplied with a second power supply potential, and the common node, for selectively connecting the common node to either the first power supply potential node or the second power supply potential node, in response to a control signal.

Multi-bank semiconductor memory device having an output control circuit

A synchronous semiconductor memory device which prevents to misread due to the parasitic capacitance is disclosed. A synchronous semiconductor memory device of the present invention comprises memory cells for storing data therein, sense amplifiers coupled to the memory cells and pairs of data lines coupled to the sense amplifiers. The data lines extend to one direction so that the data lines are substantially parallel to each other. The pairs of data lines include first pairs of data lines and second pairs of data lines located between the first pairs of data lines. Each of the second pairs has a cross point at which each of the data lines of the pair crosses each other.

Synchronous semiconductor memory device

An output buffer circuit comprises an input terminal for receiving an input signal, an output circuit coupled to a first node for outputting an output signal in response to a potential level appeared on the first node and a bootstrap circuit coupled between the first node and the input terminal. The bootstrap circuit comprises a delay circuit for delaying the input signal to provide a delayed input signal, a first transistor for receiving a signal inverted from the input signal, a second transistor coupled for receiving the delayed input signal and controlling a the first transistor, a third transistor connected in parallel to the second transistor, a fourth transistor coupled a gate of the third transistor for receiving the input signal and a charge circuit coupled between the delay circuit and the first node for supplying an electric charge to the first node. The charge circuit is activated in response to the potential level appeared on the first node and the delayed input signal.

Bootstrapped high-speed output buffer

A semiconductor memory device according to the present invention comprises a first and second nodes, a first power supply for supplying a supply power potential to the first node, a memory cell for storing data therein; a bit line connected to the memory cell, a sense amplifier connected to the second node, for amplifying a potential of the bit line; a switching circuit connected between the first and second nodes, for coupling the first node with second node in response to a first control signal and substantial disconnecting the first node from the second node in response to a second control signal, a detecting circuit for detecting a potential of the second node and outputting a detection signal when the potential of second node is substantialy equal to the supply power potential, a control circuit applied an address signal having a first or second logic level thereto, for outputting the first control signal in response to the address signal being the first logic level and outputting the second control signal in response to the detection signal after the address signal being the second logic level.

Growing community of inventors

Miyazaki, Japan

Norihiko Satani