Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Socionext Inc.

Norihiko Mizobata

Takuya Sayama

Satoshi Takahashi

Masaru Uya

Mikihiko Yamada

Takeshi Kawano

Takeshi Ichise

Akihiro Suzuki

Makoto Hirano

Kazuhisa Tanaka

Shouichi Gotoh

Masahiro Takeuchi

Hironori Kubo

Taizo Tsujimoto

Masazumi Yamada

Satoshi Okamoto

Hiroyuki Iitsuka

Ryogo Yanagisawa

Shirou Yoshioka

Shoichi Goto

Taizou Tsujimoto

Tomoya Sato

Tomohiro Okuno

Taku Arakawa

Wakahiko Okazaki

Tomokuni Yamaguchi

Yuka Takahashi

A semiconductor integrated circuit operates with a voltage supplied from a first power supply IC to transmit and receive data to and from an external memory. The semiconductor integrated circuit includes: an interface circuit operating with a voltage supplied from a second power supply IC and accessing the external memory to transmit and receive data to and from the external memory; a determination circuit which determines, based on a result of the access by the interface circuit, an AC timing specification between the external memory and the interface circuit to generate control information for controlling an output voltage of the second power supply IC in accordance with the AC timing specification; and a voltage control circuit which controls the output voltage of the second power supply IC in accordance with the control information.

Method for controlling power supply voltage in semiconductor integrated circuit

Semiconductor integrated circuit, and data interface system provided with same, which provides for dynamic control of the supply voltage

In a video audio processing device, a signal processing block () includes an instruction memory () and performs signal processing in accordance with a program loaded into the instruction memory. A main storage section () has a self-refresh function and is accessible from the signal processing block. An auxiliary storage section () stores the program for making the signal processing block perform the signal processing. Upon receipt of a standby instruction, a control section () performs control in such a manner as to transfer the program from the auxiliary storage section to the main storage section, and set self-refresh in the main storage section, and upon receipt of a return instruction, performs control in such a manner as to cancel the self-refresh in the main storage section, load the program from the main storage section to the instruction memory in the signal processing block, and activate the signal processing block.

Video audio processing device and standby and return method thereof

Disclosed is an integrated circuit device comprising a startup operation circuit () for carrying out processing necessary for startup and a post-startup operation circuit () for carrying out a main operation after completion of the processing necessary for startup, wherein the post-startup operation circuit () has an operation guaranteed temperature whose lower limit is higher than a lower limit of an operation guaranteed temperature of the startup operation circuit (), and the post-startup operation circuit () starts the main operation after a temperature of the integrated circuit device exceeds a threshold temperature which is equal to the lower limit of the operation guaranteed temperature of the post-startup operation circuit ().

Integrated circuit device, method of controlling operation of integrated circuit device, and method of fabricating integrated circuit device

In a packet data processing determination apparatus (DBA) for respectively and sequentially determining a plurality of packet data (P) composing an inputted transport stream (TS), a packet data storage section () stores the packet data (P) for a predetermined time period in the order in which they came. A stored packet data identifying section () reads identification information (PIDe) from the stored packet data (P). A target packet data determining section () compares the read identification information (PIDe) with predetermined process information (PIDd) to determine whether the packet data (P) is to be processed.

Packet data processing determination apparatus

In a multi-format transport stream decoder that performs a desired process on first transport streams of different formats to generate a second transport stream, a process request information input unit (APR) is supplied with process target packet data (Pi) and process request information (ScW) indicative of process details. A stream identification information providing unit (TSRi) provides stream identification information (TSID). A packet data retaining and identifying unit (DBA) retains each pieces of first packet data (Pi), and compares the stream identification information (TSIDe) and packet data identification information (PIDe) of the first packet data (Pi) with the process request information (ScW) to determine whether the information is to be processed.

Multi-format transport stream decoder

With a temporary operating unit being operating, a user provides a boot timing using a boot timing instructing unit. This causes a CPU to compute a boot preparation timing based on the boot timing, and store the boot timing and boot preparation timing to a boot timing memory. At this time, a timer begins a time-keeping operation. After that, the user turns off the power to the temporary operating unit. A boot preparation instructing unit determines whether or not the time being measured by the timer coincides with the boot preparation timing stored in the boot timing memory. When the time measured by the timer coincides with the boot preparation timing stored in the boot timing memory, the boot preparation instructing unit provides the CPU with a boot preparation instruction. This turns on the power to the temporary operating unit, and the CPU performs a boot preparation.

Boot time reducing device including boot preparation instructing unit

A demultiplexer circuit which can simultaneously demultiplex plural pieces of input data while minimizing the circuit scale. The demultiplexer circuit includes an input line identification information addition circuitfor giving input line identification information to input data which have data identification information and are inputted through plural input lines, respectively; a multiplexerfor outputting the input data which have been given the input line identification information, respectively, by the input line identification information addition circuitthrough one common line; a filterfor filtering the data outputted from the multiplexeron the basis of the input line identification information and the data identification information at one time; and a filter tablethat contains filtering conditions which are used in the filter

Demultiplexer circuit

A data transmitter for detecting a reference time stamp for use in reproducing a system clock from a transport packet data of a first transport stream, adding the detected reference time stamp as a header information to the transport packet data, converting the transport packet data and the header information into a second transport stream, and transmitting the second transport stream.

Data transmitter and data receiver

A demultiplexer is provided with a PID extractor for extracting a PID of each TS packet from an inputted transport stream; a PID comparator for detecting whether or not the extracted PID matches any of PIDs which are set on a PID table, and outputting an entry number of the PID table where the corresponding PID is set, as a matching PID entry number, when a match is detected; a packet selector for selecting TS packets whose PIDs are detected by the PID comparator; and a data storage controller for determining an area in a memory where each TS packet is to be stored, according to the matching PID entry number; wherein TS packets having different PIDs are multiplexed and stored into a video data storage area in the memory. Therefore, when plural kinds of video data are included in the same program on digital broadcasting, these plural kinds of video data can be reproduced simultaneously.

Data selection/storage apparatus and data processing apparatus using data selection/storage apparatus

The stream processor of the present invention includes: a selection section and first to fifth processing sections. In the selection section, a plurality of inputs are associated with a plurality of outputs according to control from outside so that streams sent to the plurality of inputs are passed to the associated outputs. The first processing section sends a first stream to the first input among the plurality of inputs. The second processing section sends a second stream to the second input among the plurality of inputs. The third processing section receives a stream from the first output among the plurality of outputs. The fourth processing section receives a stream from the second output among the plurality of outputs. The fifth processing section receives a stream from the third output among the plurality of outputs, subjects the received stream to predetermined processing, and sends the processed stream to the third input among the plurality of inputs.

Stream processor

A digital broadcast data receiving apparatus comprises a plurality of broadcast data receiving units for receiving digital broadcast data supplied from a plurality of digital broadcast data sources, respectively and a parallel receiving unit for receiving, from the digital broadcast data output from the plural broadcast data receiving units, object program broadcast data which are multiplexed digital broadcast data including program broadcast data relating to an object program broadcast to be viewed by the viewer, and received broadcast data which are digital broadcast data output from the broadcast data receiving unit different from the broadcast data receiving unit which outputs the object program broadcast data. The parallel receiving unit performs the following processes according to time division multiplexing: a process of extracting program broadcast data relating to the object program broadcast to be viewed from the object program broadcast data, and a process of extracting data including information to be obtained even when the viewer does not watch the broadcast, from the received broadcast data. Therefore, it is possible to realize a receiving apparatus Which receives digital broadcast data supplied from plural input sources at the same time, and obtains necessary data included in the digital broadcast data supplied from one of the input sources while displaying the digital broadcast data supplied from the other input source, on a television receiver.

Digital broadcast data receiving apparatus

A digital communication system comprises a transmitter for sequentially transmitting predetermined format data; and a plurality of receivers each including a data selecting apparatus for selecting required data from received data group and outputting selected data. The transmitter transmits data to the receivers in one of a first transmission mode having group destination directing information indicating that the data is to be transmitted to a receiving group consisting of predetermined receivers of the plurality of receivers, group specifying information for specifying a receiving group of receiving groups to which the data is to be transmitted, and in-group identification information for identifying a receiver in an arbitrary receiving group to which the data is to be transmitted, a second transmission mode having the group destination directing information and the group specifying information are included in the data, and a third transmission mode having the group destination directing information.

Digital communication system, transmitter, and data selector

A data match detecting apparatus which sequentially receives input data comprising plural fields, comprises parameter storage which contains a parameter group comprising plural parameters which are checked to detect a match between the plural fields and the plural parameters; parameter selector for selecting a parameter corresponding to a field input as the input data from the parameter storage and outputting the selected parameter; data comparator for checking match between the parameter output from the parameter selector and the input data; a comparison result storing circuit initialing its storage content to match before a first field of the input data for which match detection should be performed is input, storing a comparison result of a comparison result decider when there is an input field, and outputting its storage content when all the fields of the input data for which match detection should be performed have been input; and the comparison result decider storing match in the comparison result storage when the storage content of the comparison result storage and the comparison result of the data comparator are match.

Data match detecting apparatus, and data selecting apparatus

A video memory stores a plurality of image data, and an attribute storage means stores image attributes indicating whether or not the respective image data require expansion of a luminance range. An image data conversion means receives an image data digital signal output from the video memory and an image attribute signal output from the attribute storage means. When the image attribute signal provides an instruction to expand the luminance range, the image data conversion means outputs, to a display unit, a display data analog signal representing a higher luminance value, as compared with the display data analog signal to be output therefrom when the image attribute signal provides no instruction to expand the luminance range.

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Habikino, Japan

Norihiko Mizobata