Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Norihide Kinugasa

Kenichi Tatehara

Yoshio Nirasawa

Hideo Hamaguchi

Sachi Ota

Mitsuhiko Otani

Naohisa Hatani

Narutoshi Kanazawa

Koichi Yoshimura

Yoshimitsu Saka

Shiro Dosho

Naoki Okamoto

Takashi Morie

Hitoshi Kobayashi

Shinichi Ogita

Akio Yokoyama

Mamoru Arayashiki

Masaomi Toyama

Hikaru Masui

Hisashi Takahashi

Michiyo Yamamoto

Yuji Amano

Makoto Kawajiri

Toshiaki Ioi

Haruhiko Mizuno

Takayasu Kitou

Katsumi Hironaka

Each of n signal transition detection sections detects a transition of the signal level of at least one of a first input signal or a second input signal corresponding to the signal transition detection section. A time-division control section outputs a control pulse according to a system clock when a signal transition is detected by at least one of the n signal transition detection sections. Each of n output switching sections outputs either the first or the second input signal corresponding to the output switching section as a multiplexed signal according to the control pulse.

Time-division multiplexer and signal transmission apparatus

A variable delay circuit successively delays an input clock to generate a plurality of delayed clocks having different phases. A phase comparison circuit receives a first reference clock, which is either one of the delayed clocks or the input clock, and a second reference clock, which is one of the delayed clocks and whose phase lags behind that of the first reference clock, specifies a validated interval for the second reference clock, and compares the phases of the first and second reference clocks according to voltage levels of the first and second reference clocks only during the validated interval. A delay control circuit controls a delay time in the variable delay circuit according to a result of the comparison obtained by the phase comparison circuit.

DLL circuit, imaging device, and memory device

There is provided a spike noise eliminating circuit that can eliminate reliably spike noise having a predetermined pulse width or smaller and transmit and output precisely a signal having a pulse width larger than the predetermined width. Spike noise in the input signal is eliminated by: detecting a coincidence in level of the input signal and a first delay signal obtained by delaying the input signal by a maximum pulse width of noise to be eliminated as a delay amount; and sampling the input signal or a second delay signal obtained by delaying the input signal by a certain period of time based on a signal obtained as a result of detecting the coincidence in level.

Spike noise eliminating circuit, digital system using the same, and IIC bus

A display panel control circuit includes a voltage controlled oscillator (VCO) for outputting a clock signal, a first-panel horizontal system pulse generation section, a second-panel horizontal system pulse generation section, a vertical system pulse generation section which is commonly used among the first and second panels, a phase comparator, and a smoothing element. The first-panel horizontal system pulse generation section and the second-panel horizontal system pulse generation section respectively generate a reference signal of a first-panel horizontal system output group and a reference signal of a second-panel horizontal system output group from signal VCOCLKoutput from the VCO. Thus, it is possible to simultaneously drive two different panels.

Control circuit for displaying the same video simultaneously to two or more panels

A power-on reset circuit of the present invention comprises: a first p-channel MOS transistor having the gate and the drain which are grounded and having a substrate which is connected to a power supply; a first resistor which is inserted and connected between the above-mentioned power supply and the source of the above-mentioned first p-channel MOS transistor; a first inverter having an input terminal which is connected to the source of the first p-channel MOS transistor; and a power-on reset signal output terminal which is connected to an output terminal of the first inverter.

Power-on reset circuit

An influence of a switching noise caused by a horizontal shift clock to an oscillation frequency of a voltage controlled oscillator should be eliminated, to prevent an image shift in a PAL skip period. For this purpose, an odd number line horizontal shift clock from an odd number line horizontal shift clock generator and an even number line horizontal shift clock from an even number line horizontal shift clock generator are switched by a horizontal shift clock switching circuit, to be input to a color LCD panel. The horizontal shift clock switching circuit selects and outputs either the odd number line horizontal shift clock or the even number line horizontal shift clock according to a line identifying signal, in a normal period. By contrast, in a PAL skip period a selecting state of the shift clock is inverted immediately upon start of a PAL skip period, from a selecting state right before the start of the skip period, and the selecting state is again inverted in half a cycle of a horizontal scanning period.

Horizontal shift clock pulse selecting circuit for driving a color LCD panel

A PLL circuit that makes a voltage-controlled oscillator converge to a stable state within a short time and generates a clock signal with high stability even when discontinuity occurs in the period of a reference input signal is provided. The PLL circuit has a voltage-controlled oscillator for outputting a clock controlled, a first counter reset by the reference input signal having one period longer than a reference period within a predetermined period for outputting a first signal, a second counter for outputting a second signal, a reset pulse generating circuit for resetting the second counter, a loop filter for holding and outputting the control voltage varied by a phase error signal and a discontinuous input detecting part for detecting the reference input signal input initially after its period becomes longer than the reference period.

PLL circuit and image display device

A laser diode driving device of the present invention can appropriately shorten the rising time and the falling time of a laser diode drive current in a range from a small current region to a large current region. In synchronization with the addition of an original input current from an input constant current source to the laser diode drive current amplifier, a differentiated current is added to the input current through a differentiation circuit and a pull-in type V-I conversion circuit, whereby the rising of a laser diode drive current is made abrupt. Furthermore, by increasing a gate potential of an input PchMOS transistor constituting the laser diode drive current amplifier by a differentiation circuit and a push-out type V-I conversion circuit in synchronization with the disconnection of an input current, the falling of a laser diode drive current is made abrupt.

Laser diode driving device

In order to improve the robustness against electrostatic discharge, when power source terminal and ground terminal are open, of a semiconductor device having a first, a second and a third inverter that are connected in a cascade arrangement, the semiconductor device is provided not only with a first input protection circuit for guiding positive electrostatic discharges, that are applied from outside to a signal input terminal, to a power source line, and a second input protection circuit for guiding negative electrostatic discharges, that are applied from outside to the signal input terminal, to a ground line, but also an internal protection circuit for guiding electrostatic discharges that have been guided by the first input protection circuit to the power source line and flow from a P-channel MOS transistor in the second inverter towards the third inverter, to the ground line.

Semiconductor device

In a front end that has a filter circuit and is used for a communication system having an asymmetric communication channel in which upstream and downstream data rates are different, a filter circuit for received signals, which is for filtering received signals, and a filter circuit for transmitted signals, which is for filtering transmitted signals, are provided. The filter circuit for received signals has an amplifier block including a plurality of amplifiers, a capacitor block including a plurality of capacitors and being connected to the plurality of amplifiers included in the amplifier block, and a first and a second resistor blocks each including a plurality of resistors. Either one of the first or the second resistor block is selectively switched so as to be connected to the amplifier block by a resistor block-switching circuit. The circuit scale is reduced since only one amplifier block and one capacitor block are commonly used for two kinds of filter circuits.

Filter circuit, front end of communication system including the filter circuit, and communication device including the same

To tune the center frequency of a gm-C filter, which is a bandpass filter with a narrow bandwidth, to a target frequency, only while the filter is being tuned, the original circuit configuration of the filter is replaced with an alternative configuration that realizes a high signal-to-noise ratio. A characteristic tuner generates and inputs an impulse signal, pulse signal or step signal to the filter being tuned and thereby detects and adjusts the center frequency of the filter. And the tuning result is stored on a nonvolatile memory for future reuse. When the filter is operated, the characteristic tuner stops operating to cut down the power dissipation.

Automatic filter tuning control system

The digital-analog converter circuit includes: a high-order D-A converter circuit unit ( ) for outputting a first voltage (Va) and a second voltage (Vb) both resulting from D-A conversion of the high-order five bits of a 13-bit input code to first and second output nodes ( ) through two buffers ( ) having the same characteristics, respectively; a low-order D-A converter circuit unit ( ) for receiving the voltages on these two output nodes as reference voltages of an R-2R ladder circuit ( ) and conducting D-A conversion of the low-order eight bits of the input code for output to a third output node ( ); a sample-and-hold unit ( ) for selectively sampling and holding the voltage on the third output node ( ), i.e., the D-A conversion output of the 13-bit input code, according to a value of the input code; and an output unit ( ) for multiplying the sampled and held D-A conversion output voltage by a gain with respect to an arbitrary central voltage. Thus, a D-A converter circuit capable of outputting a desired analog voltage with high accuracy even when a large number of bits are converted is implemented with a small chip area.

High-precision D-A converter circuit

A compact, inexpensive circuit for generating several stable reference signals from several burst signals is provided. The circuit comprises a first oscillator using a quartz oscillator; a second oscillator with a variable oscillation frequency having a range broader than that of the first voltage-controlled oscillator; a first frequency divider for dividing a frequency of an output signal of the first oscillator by j; a second frequency divider for dividing a frequency of an output signal of the second oscillator by k; a first phase comparator for comparing a phase of an output signal of the first frequency divider with a phase of an output signal of the second frequency divider; a first lowpass filter for smoothing an output signal of the first phase comparator and returning the smoothed signal as feedback to a control terminal of the second oscillator; a second phase comparator for comparing a phase of an output signal of the second oscillator with a phase of the burst signal; and a second lowpass filter for smoothing an output signal of the second phase comparator and returning the smoothed signal as feedback to a control terminal of the first oscillator. The continuous reference signal with the desired frequency is obtained from the output signal of the second oscillator.

Circuit for generating a reference signal

Provided is a two-step parallel A/D converter capable of operating at a higher speed than in the prior art and easily performing correction of upper bit data. An upper limit voltage V.sub.H of a voltage range for lower bit conversion is amplified on the basis of a median voltage V.sub.M of the voltage range by a second differential amplifier, and the amplified voltage is set to a high level reference voltage SUB.sub.H for lower bit conversion. A lower limit voltage V.sub.L of the voltage range is amplified on the basis of the median voltage V.sub.M by a third differential amplifier, and the amplified voltage is set to a low level reference voltage SUB.sub.L for lower bit conversion. A voltage V.sub.IN of an input analog signal is amplified on the basis of the voltage V.sub.M by a first differential amplifier, and lower bit data is obtained from a position between the voltage SUB.sub.H and the voltage SUB.sub.L which is occupied by an obtained voltage SUB.sub.IN. The voltages SUB.sub.H and SUB.sub.L are not changed by the voltage V.sub.IN of the input analog signal. Consequently, a settling time can be shortened more than in the prior art.

Growing community of inventors

Kyoto, Japan

Norihide Kinugasa