Kabushiki Kaisha Toshiba

Noriaki Suzuki

Junichi Miyamoto

Nobuaki Ohtsuka

Yuuichi Tatsumi

Hidenobu Minagawa

Hitoshi Ohta

Kazuhiko Satou

That surface portion of a semiconductor substrate which is adjacent to a buried source region formed in the substrate is covered with an offset side wall to suppress expansion of a channel beneath the offset side wall. In addition, buried source regions in the form of offset side walls are formed on the two sides of a drain region having one non-offset side wall to prevent a write or read error in unselected memory cell transistors on both sides of a selected memory transistor either in a data write or in a data read.

Semiconductor memory device using MONOS type nonvolatile memory cell

An improved semiconductor memory device having a memory array, a dummy cell and a redundancy cell column is disclosed. At least one dummy capacity cell is connected to the reference bit line to which the dummy cell is connected, and also to a redundancy bit line to which redundancy cells are connected. Therefore, since a capacity on the reference bit line is roughly equalized to that on the redundancy bit line by these dummy capacity cells, it is possible to prevent erroneous potential level determination by a sense amplifier for comparing both the potentials on both the bit lines, without being subjected to the influence of supply voltage fluctuations.

Redundant semiconductor memory device

Growing community of inventors

Yokohama, Japan

Noriaki Suzuki