Fujitsu Corporation

Noriaki Ono

Minoru Usui

Hiroyuki Fujiyama

Hideaki Tomatsuri

Yasushi Nagano

A data processing device exchanges data between a memory and an external bus master. The memory is connected to the data processing device via a first bus so as to store data. The external bus master is connected to the data processing device via a second bus so as to process data. The data processing device comprises a bus-transmission control unit accessing the memory via the first bus in response to a request to access the memory made by the external bus master via the second bus.

Data processing device accessing a memory in response to a request made by an external bus master

In a bus control system for generating a series of access requests from an access requesting unit, such as a CPU connected to a common bus including a data bus or an address bus, to a specific access request responding unit, the specific access request responding unit includes a next-address enable signal generating unit for sending a next-address enable signal which represents that a next address can be received, to the access requesting unit before data is transferred or inputted, in accordance with an address representing the access request from the access requesting unit when a read operation or a write operation is executed. Preferably, the access requesting unit includes a next-address enable signal receiving unit for receiving the next-address enable signal from the specific access request responding unit and for sending the next address to the specific access request responding unit. On the other hand, a bus control method executed by using the bus control system, having the construction described above, is disclosed.

Access limiting bus control system and method

Disclosed are a semiconductor device of which a block having a plurality of portions that operate based on a plurality of clocks can be designed and inspected easily, and a method of designing the semiconductor device. First and second clocks whose frequencies are mutually different are used to generate an enabling signal that is validated only during a short period including a transition edge of the second clock. The enabling signal and first clock are supplied to the second portion. The second portion synthesizes the enabling signal and first clock to substantially generate the second clock. Thus, the second portion is regarded as a portion that operates synchronously with the first clock.

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Kawasaki, Japan

Noriaki Ono