Panasonic Corporation

Noriaki Narumi

Yoshinobu Yamagami

Yasuhiro Agata

Tsuyoshi Koike

Akira Masuo

There are included first and second dynamic circuits and first and second transistors. The first dynamic circuit keeps a first dynamic node at a first level when a plurality of input signals is in a first state, and switches the first dynamic node between the first level and a second level in accordance with a first clock signal when the plurality of input signals is in a second state. The second dynamic circuit includes a compensating circuit that is provided between the second dynamic node and a second power supply and connects the second dynamic node to the second power supply so as to compensate the level of the second dynamic node when the plurality of input signals is in the second state and the first dynamic node is at a level other than the first level.

Semiconductor integrated circuit

A system LSI () having a logic circuit () and a plurality of SRAM macros () includes a power supply circuit () configured to receive a voltage (VDDP) supplied from the outside of the system LSI (), and to generate a stabilized voltage (VDDM) lower than the voltage (VDDP). An SRAM memory cell () of each of the plurality of SRAM macros () is supplied with the voltage (VDDM) generated by the power supply circuit (), and an SRAM logic circuit () of each of the plurality of SRAM macros () is supplied with a voltage (VDD) supplied from the outside. In addition, the logic circuit () is supplied with the voltage (VDD) from the outside.

Growing community of inventors

Osaka, Japan

Noriaki Narumi