Micron Technology Incorporated

Elpida Memory, Inc.

Ps4 Luxco S.a.r.l.

Other

Nec Corporation

Longitude Semiconductor S.a.r.l.

Noriaki Mochida

Scott Eugene Smith

Kallol Mazumder

Kyoichi Nagata

Takayuki Miyamoto

Yasuhiro Matsumoto

Takeshi Ohgami

Daiki Izawa

Apparatuses including a loopback circuit are disclosed. An example apparatus according to the disclosure includes a plurality of input signal receivers and a loopback circuit coupled to the plurality of input signal receivers. The loopback circuit includes a signal multiplexer and a selector. The signal multiplexer provides an input signal received at one input receiver of the plurality of input receivers as a selected signal. The selector coupled to the signal multiplexer provides a loopback signal based on the selected signal and an alleviation signal that transitions between two different states, periodically.

Timing adjustment for data input/output buffer circuits

An exemplary semiconductor device includes an internal clock circuit configured to intermittently enable and disable a clock signal while in a Maximum Power Savings Mode. The duty cycle of the enablement and disablement of the clock signal may be based on susceptibility to negative-bias temperature instability of a component of the semiconductor device. The clock signal may be enabled and disabled via a synchronizer.

Low power clock injection during idle mode operations

Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first memory bank including at least one first sense amplifier that is enabled responsive to a first activation signal; a second memory bank including at least one second sense amplifier that is enabled responsive to a second activation signal; and a control circuit that receives a control signal. The control circuit includes a delay circuit that provides a delayed control signal by delaying the control signal, a first sense amplifier control circuit coupled to the first delay circuit and provides the first activation signal respective to the delayed control signal when the first memory bank is designated, and a second sense amplifier control circuit coupled to the delay circuit and provides the second activation signal respective to the delayed control signal when the second memory bank is designated.

Timing control circuit shared by a plurality of banks

The present invention is provided with; subword drivers SWD for driving subword lines SWL, a selection circuit for supplying either negative potential VKKor VKKto the subword drivers SWD, and memory cells MC that are selected in the case when the subword line SWL is set to an active potential VPP and are not selected in the case when the subword line SWL is either a negative potential VKKor VKK

Semiconductor device including subword driver circuit

Disclosed herein is a device includes first and second memory mats. The first memory mat includes first and defective memory cells and first local bit lines coupled to a first global bit line. Each of the first local bit lines is coupled to associated ones of the first memory cells, one of the first local bit lines is further coupled to the defective memory cell. The second memory mat includes second and redundant memory cells and second local bit lines coupled to a second global bit line. Each of the second local bit lines is coupled to associated ones of the second memory cells, one of the second local bit lines is further coupled to the redundant memory cell. The device further includes a control circuit accessing the redundant memory cell when the access address information coincides with the defective address information that designates the defective memory cell.

Semiconductor device having hierarchically structured bit lines

The present invention is provided with: subword drivers SWD for driving subword lines SWL, a selection circuit for supplying either negative potential VKKor VKKto the subword drivers SWD, and memory cells MC that are selected in the case when the subword line SWL is set to an active potential VPP and are not selected in the case when the subword line SWL is either a negative potential VKKor VKK

Disclosed herein is a semiconductor device comprising local bit lines, a global bit line, local switch control lines, main switch control lines, hierarchical switches controlling electrical connections between the local bit lines and the global bit line in response to potentials of the local switch control lines, local switch drivers driving the local switch control lines in response to potentials of the main switch control lines, and main switch drivers selectively activating the main switch control lines.

Semiconductor device and data processing system

A semiconductor device having hierarchical bit lines is disclosed, which comprises: a first global bit line; first and second local bit lines coupled in common to the first global bit line; first and second power lines; a first transistor coupled between the first local bit line and the first power line; a second transistor coupled between the second local bit line and the second power line; a third transistor coupled between the first and second power lines.

Semiconductor device having hierarchical bit line structure

A first data amplifier connects to a first memory cell identified by an X-address signal and a selection signal obtained by predecoding a Y-address signal. A second data amplifier connects to a second memory cell identified by the X-address signal and a delayed selection signal obtained by delaying the selection signal. A generator generates a delayed operation clock signal by delaying an operation clock signal of the first data amplifier. A timing controller receives a first control signal for controlling an operation of the first data amplifier and a second control signal for controlling an operation of the second data amplifier, outputs the first control signal to the first data amplifier at a timing according to the operation clock signal, and outputs the second control signal to the second data amplifier at a timing according to the delayed operation clock signal.

Semiconductor device

A semiconductor device includes a plural number of sense amplifiers that sense at least two data in parallel and that operate under a first frequency, and a multiplexer that operates under a second frequency higher than the first frequency and that sequentially serially outputs the data sensed in parallel. The semiconductor device also includes a driver circuit having a latch circuit connected to an output of the multiplexer, and an output driver circuit connected to the latch circuit and operating under the second frequency. The voltage of a power supply of the sense amplifiers is the same as the voltage of a power supply of the output driver circuit. The power supply of the sense amplifiers and the power supply of the output driver circuit are connected to respective different power supply lines.

To comprise a memory cell array, a read amplifier that is provided outside the memory cell array and amplifies data read from the memory cell array, a write amplifier that is provided outside the memory cell array and amplifies data to be written in the memory cell array, and a relief storage cell that is provided outside the memory cell array and connected to an input terminal of the read amplifier and an output terminal of the write amplifier via a switch. With this configuration, a timing of operating a main amplifier and the relief storage cell does not need to be changed depending on a position of a memory block. Further, the number of components required for connecting to the relief storage cell can be minimized.

Growing community of inventors

Tokyo, Japan

Noriaki Mochida