Matsushita Electric Industrial Co., Ltd.

Noriaki Minamida

Hidetoshi Suzuki

Yukihiro Fujimoto

Toshihiro Ishikawa

Yasuyo Maruwaka

In the equation for obtaining the number of increase or decrease bits Zij on each channel for each frame defined in the specification TS25.212 Ver.3.1.0 of 3GPP that is a standard organization of the 3rd generation digital mobile communication, Ndataj is multiplied by a calculation result of RMm*Nmj/RMm*Nmj. According to a rate matching calculation method of the present invention, the correction value 1/Ndataj is added in order to prevent the added whole value of the equation from exceeding 1 when Ndataj is multiplied.

Rate matching calculation method and rate matching apparatus

Voice coding section generates voice data and image coding section generates image data, an error decision bit is added to each of these data and these data are multiplexed and transmitted. On the receiving side, reception section receives this multiplexed data, separation section separates the multiplexed data into the voice data and image data. This voice data and image data are subjected to transmission error decision by voice reception code error decision section and image reception code error decision section , respectively. Then, voice decoding section decodes the voice data and image decoding section decodes the image data.

Apparatus and method for image/voice transmission

In a multimedia radio communication system in which a plurality of types of information media are combined, more than two terminals are connected to one terminal interface adapter connected to a mobile station apparatus. In this way, more than two sorts of information are multiplexed and communicated by radio between one mobile station and a base station.

Multimedia terminal device

An arithmetic unit includes an arithmetic and logic circuit having n bits and capable of controlling the execution of either addition or subtraction by responding to a signal indicative of a positive or negative sign of a result of one preceding calculation, a register of n bits for temporarily storing data delivered out of the arithmetic and logic circuit, a register of n bits for delivering a divisor to the arithmetic and logic circuit, a shift register of n stages for sequentially storing signals indicative of a positive or negative sign of results of calculation by the arithmetic and logic circuit, and a shifter for shifting data of the register by one bit to the left and inserting data of the most significant bit of the shift register into the least significant bit to provide an output which in turn is delivered to the arithmetic and logic circuit. A conventional shifter having a bit length of 2n can be replaced with the shifter having a bit length of n and the shift register having a bit length of n.

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Kanazawa, Japan

Noriaki Minamida