Nec Corporation

Nec Electronics Corporation

Renesas Electronics Corporation

Nec Electroincs Corporation

Noriaki Kodama

Kohji Kanamori

Teiichirou Nishizaka

Isao Katayama

Yoshihiro Matsuura

Kaoru Ishihara

Yasushi Harada

Naruaki Minenaga

Chihiro Oshita

Toshikatsu Jinbo

Takuji Onuma

Kenichi Hidaka

Junichi Suzuki

Kiyokazu Ishige

Hiroyuki Kobatake

Noriyuki Ohta

Atsunori Miki

Kazuhisa Ninomiya

Akio Toda

Shinji Fujieda

Yasuhide Den

A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode.

Non-volatile semiconductor memory device

A semiconductor memory device includes a first anti-fuse element and a second anti-fuse element, respectively composed of a transistor, wherein the first anti-fuse element and the second anti-fuse element are configured so as to be concomitantly programmable, respectively formed in P-wells on a substrate, and the adjacent P-wells are isolated by N-wells of an opposite conductivity type, formed therebetween.

Semiconductor memory device and a method of controlling a semiconductor memory device

According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.

Semiconductor storage device, semiconductor device, and manufacturing method therefor

Obtained is a highly-reliable non-volatile memory without increasing the area of a memory cell or adding a step to a CMOS process. The non-volatile memory includes an SRAM cell configured of 6 MOS transistors, a first word line electrically connected to the gate of a first transfer MOS transistor, and a second word line electrically connected to the gate of a second transfer MOS transistor. During a write operation of a first PMOS transistor, a drive circuit applies a positive voltage whose absolute value is not larger than a junction breakdown voltage to an n-type well as well as the sources of first and second PMOS transistors, concurrently applying the positive voltage to the first word line and a ground voltage to the second word line and a first data line.

Semiconductor memory device

Semiconductor device of a charge storage type

A nonvolatile semiconductor memory device includes a substrate, a central structure, a second gate insulating film, a floating gate, and a control gate. The substrate has a trench. The central structure is formed so as to be embedded in the trench and protruded from the substrate. The second gate insulating film is formed on the substrate so as to be contact with the central structure. The floating gate is formed on the second gate insulating film. The control gate is formed so as to cover the floating gate through a insulating film;. The central structure includes an assistant gate and a first gate insulating film which is formed such that the assistance gate is surrounded with the first gate insulating film. The floating gate is formed in a side wall shape on the side surface of the central structure.

Nonvolatile semiconductor memory device including an assistant gate formed in a trench

A nonvolatile memory device includes source and drain regions formed in a semiconductor substrate, and an insulating film formed on a channel region between the source region and the drain region in the semiconductor substrate. The nonvolatile memory device also includes a dielectric film formed above the channel region to store electric charge, and a control gate formed on the dielectric film. Compressive stress in the channel region is equal to or less than 50 MPa.

Nonvolatile memory and nonvolatile memory manufacturing method

According to the present invention, a method for manufacturing a nonvolatile semiconductor storage device is provided in which an element separating layer and first gate insulating layer are respectively formed onto a silicon base, followed by layering and patterning of a first polysilicon layer. A second gate insulating layer for forming an ONO structure and a second polysilicon layer are then sequentially formed and patterned. After formation of a gate oxide layer, a third polysilicon layer is layered and patterned to form a gate electrode. The second and first polysilicon layers are then patterned to respectively form control gate and floating gate.

Method for manufacturing a nonvolatile semiconductor storage device

There is provided a non-volatile semiconductor memory device, including (a) a first gate insulating film formed on a channel region of a semiconductor substrate, (b) a floating gate electrode formed on the first gate insulating film, (c) a second gate insulating film formed on the floating gate electrode, (d) a control gate electrode formed on the second gate insulating film, and (e) an electric power source applying a gradually increasing voltage across the control gate electrode and the semiconductor substrate, the electric power source varying both an increment by which the voltage is increased and a period of time during which the voltage is kept constant, while data is being rewritten. The non-volatile semiconductor memory device is capable of increasing a rate at which data stored therein is deleted, without deleting data more than necessary.

Non-volatile semiconductor memory device and method of rewriting data stored in non-volatile semiconductor memory device

A plurality of memory cells are arranged in lattice arrangement to form a memory cell array. Each of the memory cells is provided with a source. Data in the memory cell can be electrically written and erased. Sources of all the memory cells are connected in common. Also, a source voltage control circuit having two or more kinds of load characteristics is connected to the sources connected in common. According to a load characteristics selected from a plurality of load characteristics, source voltage of the memory cell is controlled.

In a memory cell including a floating gate, a gate insulation film and a control gate, after removing injected charges from the floating gate with tunneling currents through the gate insulation film, charges are removed from the gate insulation film by applying a pair of positive and negative voltage pulses to the control gate at least one time.

Control method for non-volatile memory

A nonvolatile semiconductor memory includes a cell array prepared by arranging erasable and programmable memory cell transistors in rows and columns, word lines arranged in correspondence with the respective rows of the cell array and connected to the control gates of the memory cell transistors, digit lines arranged in correspondence with the respective columns of the cell array and connected to the drains of the memory cell transistors, source lines connected to the sources of the memory cell transistors, and a source power supply circuit for applying a source voltage to the source lines in an erase operation. This memory erases by the source voltage data in the memory cell transistors in the rows and columns of the cell array. The source power supply circuit is a circuit including a first P-channel transistor which sets a current to be supplied to the source lines to a predetermined value in the erase operation in a range wherein the source voltage is lower than a predetermined potential, and a second P-channel transistor which sets the current to be supplied to the source lines so as to decrease faster than the current decreased by the characteristic of the first transistor with an increase in source voltage in a range wherein the source voltage is higher than the predetermined potential.

Nonvolatile semiconductor memory

In a nonvolatile semiconductor device having a floating gate formed over a semiconductor substrate, a control gate formed over the floating gate, a source region and a drain region formed within the semiconductor substrate, an erase or write operation is carried out by Fowler-Nordheim tunneling, so that carriers such as electrons and holes are expelled from the floating gate to one of the source and drain regions. Thereafter, carriers of a channel current flowing between the source and drain regions are enhanced and injected into the floating gate, thus converging a threshold voltage of the device.

Nonvolatile semiconductor memory device capable of converging threshold

There is provided an involatile semiconductor memory deice comprising a virtual ground memory cell array which allows the read current to be increased without degrading the writing characteristic. A source/drain of a memory cell having a floating gate 3 is composed of a double diffusion layer comprising an n.sup.- -type diffusion layer 7 and an n.sup.+ -type diffusion layer 8, the n.sup.+ -type diffusion layer 8 overlaps with one end of the floating gate 3 and the other is provided with an offset of the n.sup.- -type diffusion layer 7.

Growing community of inventors

Tokyo, Japan

Noriaki Kodama