Hitachi, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Information Technology Co., Ltd.

Other

Hitachi Computer Engineering Co., Ltd.

Noriaki Hatanaka

Masaki Yoshinaga

Yuji Nagaya

Takashi Hashimoto

Tatsuo Mochizuki

Katsuya Sonoyama

Tsuyoshi Hirose

Tadao Kaji

Tomoaki Hirai

Takeshi Maeda

Makoto Koizumi

Hajime Aoi

Takashi Tamura

Minoru Enomoto

Tadahiko Kameyama

Yuji Soga

Noboru Kunimi

Sense current is applied in pulses, synchronized with the timing clock generated by a clock generator , to transducer in the information storage device, reducing the time-averaged value of the sense current. The recorded information on the magnetic disk medium is reproduced by the MR head as reproducing signal pulses in synchronism with the above timing clock. The amplitude of the reproducing signal pulses are proportional to the magnetic field of the magnetic disk medium . The reproducing signal pulses are sample-held by a sample-hold circuit , and after being digitized by an A/D converter , recorded data are retrieved through a demodulator circuit of a partial-response system.

Information storage device having transducers operating in a pulse mode in synchronism with a timing clock

A very-small-signal amplifier is capable of amplifying very small signals with high sensitivity up to high frequencies while simplifying the circuit, and a magnetic disk storage apparatus realizes a reading operation over a wide band up to high frequencies with high sensitivity. The signal amplifier is a modified differential circuit including a first transistor of a first conductivity type and a second transistor of a second conductivity type each having a control terminal, a terminal of the input side and a terminal of the output side. The terminals on the input side are connected in common, and a current corresponding to the voltage difference across the control terminals is allowed to flow. A very small voltage signal generated by an input signal source is applied to the control terminal of said first transistor. A bias voltage is applied to the control terminal of the second transistor. Therefore, an amplified signal corresponding to the very small voltage signal generated by the input signal source is generated at the terminal on the output side of the second transistor.

Signal amplifier and magnetic disk storage apparatus using the same

Signal amplifier apparatus and magnetic disk storage apparatus using the

A write driver for writing write data to a magnetic disk. The write driver is provided with first and second pnp type input transistors whose bases are each supplied with a pair of complementary input signals, and first and second npn type output transistor in the form of an inverted Darlington arrangement. A first resistor element is provided between the emitter of a corresponding pnp type input transistor and the collector of a npn type output transistor, whereas a second resistor element is provided between the common collector of the first and second npn type output transistors and supply voltage. The collectors of the first and second pnp type transistor are supplied with clamp voltage. Third and fourth npn type output transistors each connected to the first and second npn type output transistors in series and subjected to complementary switching control are provided to form a bridge circuit and to drive an inductive head.

Write driver circuit

A timing adjusting circuit is provided to define the operating order of a differential amplifier circuit for amplifying read-out signals and an output circuit in order to minimize changes in output DC level. A damping resistor is disposed between two magnetic head terminals and a clamp circuit in a magnetic head driving circuit. To attend to a composite head configuration, short-circuiting with a power supply and a current flowing into the magnetic head during a non-write operation are detected as abnormalities. In addition, short-circuiting and open-circuiting of the magnetic head are also detected as abnormalities. Also, a read circuit is added to a write magnetic head, in order to output read-out signals in a read mode, so that the read-out signals are utilized for detecting errors in read-out signals from an exclusively designed read head or for detecting and correcting such errors.

Read and/or write integrated circuit having an operation timing

A magnetic head circuit for a plurality of magnetic heads includes two emitter follower transistors for receiving magnetic head writing data, two differential transistors connected to the two emitter follower transistors for performing differential operation control thereover, and two resistors connected to collectors of the two differential transistors for supplying a base current to the two emitter follower transistors, and wherein the emitter follower transistors are connected in series with each other to perform differential switch operations over a magnetic head writing current. A magnetic head fly-back voltage has a clamp voltage which varies according to a writing current flowing through a pair of signal terminals. A pair of differential transistors, whose bases are connected to the pair of signal terminals and whose emitters are connected directly to each other, are operated according to a voltage appearing between the pair of signal terminals. Connected to the collectors of the pair of differential transistors are amplification transistors respectively. Connected to outputs of the amplification transistors are post-amplifiers. Such a connection configuration provides a small mirror capacitance as viewed from the bases of the amplification transistors. A high writing and reading accessing speed to the magnetic heads can be realized.

Magnetic head circuit having a write current changeover circuit with a

A current drive circuit for an induction coil is provided comprising a clamp circuit connected to the two terminals of the coil. This clamp circuit prevents the voltages of the two terminals from dropping below a reference voltage, thereby preventing decreases of the amplifier constants h.sub.FE of the transistors which are also coupled to the two terminals for a read-out operation.

Current drive circuit for an induction coil

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Chigasaki, Japan

Noriaki Hatanaka