Hitachi, Ltd.

Noriaki Hashimoto

Kanji Kubo

Chikahiko Izumi

Kazutoshi Gemma

In an encryption apparatus, prior to encryption process, information indicating whether plain text blocks are to be encrypted or not is stored in a mask register, and the number of blocks of the plain text block sequence is stored in a count register. In the encryption process, the count register is sequentially decremented, and only the plain text blocks to be encrypted are read from an input buffer in an ascending order of addresses based on the information stored in the mask register. They are encrypted by an encryption circuit and the encrypted text blocks are stored in an output buffer at the corresponding addresses to the input buffer addresses at which the plain text blocks have been stored. After the encryption process for the plain text blocks to be encrypted, only the plain text blocks not to be encrypted are sequentially read from the input buffer in the ascending order of the addresses and they are stored, without being encrypted, in the output buffer at the corresponding addresses to the input buffer addresses at which the plain text blocks have been stored.

Encryption apparatus

The present memory control system fetches data blocks from memories, fetches data corresponding to the unit of processing in the execution unit from the data blocks, and transfers the data to the execution unit. Data blocks fetched from the memories are held in first hold device. The data blocks held in the first hold device are transferred to second hold device via gate. The gate selectively transfers all or a part of data in data blocks held by the first hold device to the second hold device. When a part of data held in the first hold device is transferred, the second hold device forms data blocks by using the data previously held and the data newly transferred from the first hold device. A data fetch device fetches the data corresponding to the unit length of data processing in the execution unit from the data blocks held in said second hold device and transfers the data to said execution unit.

Memory control system

This storage system is designed to refer to a translation lookaside buffer, a buffer address array and a buffer storage in parallel. The translation lookaside buffer translates a logical address requesting memory access into a real address. The buffer storage retains part of the data retained in blocks by main storage and outputs data from M blocks in accordance with the logical address to M aligners. The buffer address array retains the addresses in MS of the data stored in each of the blocks in the buffer storage, and outputs M addresses in accordance with the logical address. A comparator compares the real addresses from the translation lookaside buffer with the addresses from the buffer address array, selects one of the outputs from the aligners, and transfers that output to a processor.

Storage system having buffer storage

A pulse train producing apparatus is arranged such that a plurality of first pulse trains are produced correspondingly to a plurality of second pulse trains to be produced so that the leading or trailing edges of the pulses of each first train are adjusted in phase according to the intended phases of corresponding edges of the pulses of a corresponding one of the second pulse trains and the pulses of each first train overlap at their leading or trailing edge portions with the trailing or leading edge portions of a different one of the first trains and two of the first pulse trains having the overlapping portions are applied for cutting away the overlapping portions of the pulses of one of the two pulse trains.

Growing community of inventors

Hadano, Japan

Noriaki Hashimoto