Infineon Technologies Ag

Siemens Aktiengesellschaft

Norbert Wirth

Ralf Schneider

Dominique Savignac

Willibald Meyer

Eric Cordes

Robert Kaiser

Christian Sichert

Zoltan Manyoki

Herbert Benzinger

Christian Stocken

Georg Erhard Eggers

Arndt Gruber

Tobias Hartner

Frank Weber

Rudiger Brede

Evangelos Stavrou

Nazif Taskin

Bernhard Ruf

A memory module includes at least one memory chip arranged on the memory module. Information about the memory module and/or the at least one memory chip arranged on the memory module can be stored directly on the memory chip, making use of a suited element, fuses or flip-flops, for example. A memory chip contains such an element for containing information relating to the memory chip and/or a memory module with which the memory chip is compatible, wherein the information containing element can be read out by means of an external processor.

Information containing means for memory modules and memory chips

The present invention provides an apparatus for signaling that a predetermined time value has elapsed, having a device for acquiring and storing the amplitude value of a clock signal at an acquisition instant in the temporal profile of the clock signal. A device is provided for continuously comparing the acquired and stored amplitude value of the clock signal with an instantaneous amplitude value of the clock signal and for outputting a comparison signal which has a first logic state if the instantaneous amplitude value of the clock signal is less than the stored amplitude value and has a second logic state if the instantaneous amplitude value of the clock signal is greater than the stored amplitude value. A device is also provided for counting the number of logic states of the comparison signal which occur after the acquisition instant, and for signaling that the predetermined time value has elapsed if the counted number of logic states is equal to a predetermined number of logic states which corresponds temporally to the predetermined time value.

Apparatus for signaling that a predetermined time value has elapsed

A method includes providing a semiconductor memory device having at least one memory cell array. The memory cell array has a multiplicity of memory cells arranged in a matrix-like manner. Each of the memory cells is assigned a physical address and an electrical address. The method also includes inputting a physical address of a memory cell that is to be addressed into an address input device of the semiconductor memory device, decoding the input physical address into the assigned electrical address of the memory cell to be addressed by an address decoder device of the semiconductor memory device, and outputting the electrical address to the memory cell array in order to address the memory cell.

On chip scrambling

A configuration for identifying contact faults during the testing of integrated circuits with a multiplicity of pins which protrude from a housing and are connected to respective pads on a semiconductor body of the integrated circuit. Pull-up or pull-down devices are connected between respective pads and input buffers and in each case hold the pads at a high or low potential by impressing a holding current, if contact has not been made with a pin associated with the pad during testing, the result being that activation of the circuit section connected to the pin is avoided.

Configuration for identifying contact faults during the testing of integrated circuits

An electronic circuit in an integrated circuit having memory cells is described. The circuit permits information to be written to particular memory cells only once, so that subsequent writing to the particular memory cells is blocked. The circuit is used in a test structure for integrated circuits on a wafer. A method for testing integrated circuits on a wafer that are connected to a test apparatus is also described. Once the supply voltage to a first circuit to be tested has been turned on, a preliminary test is carried out to ascertain parameters that need to be set. The supply voltage is then applied to a next circuit to be tested, a preliminary test is carried out, and memory cells have information written to them, until the parameters have been set for all the connected circuits to be tested. The test apparatus then carries out the actual operational test in parallel for all the connected circuits to be tested.

Integrated circuit, test structure and method for testing integrated circuits

A circuit configuration and a method for the synchronization of signals include transmitting signals in parallel through data lines and buffer-storing the signals in a synchronizing unit. A clock signal is determined from the signals of a data line and is used for synchronizing the outputting of the signals. The signals are output in the order in which the signals were read. The signals are likewise output through a plurality of data lines, the signals being output temporally synchronously. Propagation time differences are compensated due to the buffer-storage. Moreover, the clock signal is determined from the signals themselves. Consequently, the use of an additional clock signal is not necessary.

Circuit configuration and method for synchronization

The invention relates to a semiconductor module for a burn-in test configuration. The semiconductor module has a regulator which, when it is turned on, always supplies a constant low voltage to an internal circuit of the semiconductor module. The semiconductor module also contains a component which, when the burn-in voltage has been applied for a defined time period, supplies a different characteristic than when the internal voltage is applied.

Semiconductor module for burn-in test configuration

The device for generating digital signal levels can be used for signals of various logic standards. A voltage terminal for feeding an external reference voltage is provided as well as an internal voltage generator. An internal reference voltage of the voltage generator can be selectively connected to the device via a switch. The switch is actuated by a level converter. Coupling elements prevent faults caused by the supply voltage.

Circuit configuration for generating digital signals

The fuse refresh circuit for semiconductor memories has a set circuit for setting a fuse latch circuit. The fuse latch circuit is set by the set circuit in at least one refresh cycle after a voltage supply has been switched on. During the refresh cycle of the fuse latch circuit, the latter is driven with pulses in such a way that the state of the fuse latch circuit is evaluated and only an incorrectly set fuse latch circuit is set to be correct.

Fuse refresh circuit

An integrated semiconductor memory configuration includes a memory region having a plurality of segments. Each of the memory region segments have a plurality of read amplifiers and bit lines. Each two of the bit lines are connected to a respective one of the read amplifiers. A plurality of parallel data lines lead to the memory region. Each of the data lines have an end oriented toward and another end oriented away from a respective one of the memory region segments. Each of a plurality of read/write amplifier switches is disposed at one of the ends of the respective data lines. Each of a plurality of selector switches connects the read/write amplifier switch disposed on the end of a respective one of the data lines oriented toward the memory region segment to a respective one of the read amplifiers of the memory region segment.

Integrated semiconductor memory configuration

An integrated semiconductor memory array includes a memory region, a writing buffer memory associated with the memory region, a writing pointer and an input buffer associated with the writing buffer memory, a reading buffer memory associated with the memory region, a reading pointer and an output buffer associated with the reading buffer memory, and a control device being formed of a memory control circuit and a data flow control circuit. A reading column address decoder controlling the reading pointer is associated with the reading buffer memory. A reading address control unit is connected to the reading column address decoder, and a reading address register is connected to the reading address control unit. A writing column address decoder controlling the writing pointer is associated with the writing buffer memory. A writing address control unit is connected to the writing column address decoder, and a writing address register is connected to the writing address control unit. A line address decoder is provided in the memory control circuit or in the memory region and is triggerable by the reading address control unit and the writing address control unit.

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Unterschleissheim, Germany

Norbert Wirth