Stmicroelectronics N.v.

Robert Boschgmbh

Stmicroelectronics S.a.

Siemens Aktiengesellschaft

Alcatel

Technische Universitat Kaiserslautern

Tu Kaiserslautern

Norbert Wehn

Torben Brack

Frank Kienle

Friedbert Berens

Christian Weis

Andre Guntoro

Taha Ibrahim Ibrahim Soliman

Leonardo Luiz Ecco

Chirag Sudarshan

Franck Gilbert

Michael J Thul

Soeren Hein

Wolfgang Meier

Alexander Worm

Timo Lehnigk-Emden

Valentin Grigorovici

Katharina Anna Zweig

Christian De Schryver

Heiko Michel

Deepak Molly Mathew

Christian Brugger

Cem Derdiyok

Matthias Jung

Franck Kienle

Molly Mathew Deepak

A memory device comprising a plurality of memory cells situated in a first cell field, multiple first bit lines, each respectively connected to multiple memory cells of the first cell field to enable access to the memory cells via the bit line, and multiple sense amplifier pairs which respectively comprise a first and a second sense amplifier. Each first bit line is assigned to a sense amplifier pair, each first bit line being connected to a respective first semiconductor switch element, through which the bit line is electroconductively connectible to and insulatable from the first sense amplifier of the sense amplifier pair, to which the bit line is assigned. Each first bit line is connected to a respective second semiconductor switch element, through which the bit line is electroconductively connectible to and insulatable from the second sense amplifier of the sense amplifier pair, to which the bit line is assigned.

Memory device and method for performing consecutive memory accesses

A memory device comprising a cell field having memory cells, N bit lines, which are respectively connected to at least one of the memory cells of the cell field, N being a whole number greater than one, N sense amplifiers; a bit shift circuit, which has S switch element rows, S being a whole number greater than one and a row number in the range from zero to S−1 being assignable to each switch element row. Each switch element row includes at least one semiconductor switch element connected to one of the bit lines and one of the sense amplifiers. Switch elements of each row connect all bit lines, whose bit line number is smaller than or equal to N minus the row number, to sense amplifiers, so that the respective sense amplifier number is equal to the respective bit line number plus the row number.

Memory device and method for shifting memory values

The present invention relates to a computer-implemented method and a system for determining co-occurrences in at least one graph with n vertices and E edges, wherein each edge is defined by a pair of vertices, the method comprising: storing a binary adjacency matrix representing a first graph in a memory; performing a calculation step for the first graph, wherein the calculation step comprises: loading a block of at most K consecutive rows of the binary adjacency matrix from the memory and storing each row into one of K caches; streaming each of the subsequent uncached rows of the binary adjacency matrix from the memory; reading pairs of rows comprising a streamed row and each one of the cached rows; computing the logical conjunction between each couple of elements of the rows at the same position in the rows for each read pair of rows; and adding the results of the logical conjunction for all the couples of elements in each read pair by means of one-bit adders to obtain the co-occurrence, wherein the calculation step is repeated for consecutive blocks of rows in the binary adjacency matrix until all the pairs of rows of the binary adjacency matrix have been read.

Automated determination of networks motifs

A method and a related DRAM controller for refreshing a DRAM with an external multi-row, multi-bank refresh function based on optimized command sequences involves determining, at initialization time of the DRAM, inter-operation timing parameters for the external multi-row, multi-bank refresh function, determining optimized timing parameters for row-level activation (ACT) and pre-charge (PRE) commands, and applying the optimized timing parameters for the row-level ACT and PRE commands for refreshing the DRAM with the external multi-row multi-bank refresh function. The auto-refresh function of an SDRAM is replaced.

Using runtime reverse engineering to optimize DRAM refresh

A method of decoding a received systematic code encoded block corresponding to an original block of information, wherein the received systematic code encoded block may include soft systematic values, may include detecting an error condition in the received systematic code encoded block. The method may also include decoding the received systematic code encoded block for retrieving the original block of information if the error condition in the received systematic code encoded block is detected and processing the soft systematic values to retrieve the original block of information instead of the decoding if the error condition in the received systematic code encoded block is not detected.

Method and device for decoding a received systematic code encoded block

The method includes defining from all the check nodes at least one group of check nodes mutually connected through at least one second variable node defining an internal second variable node. The method includes performing for each group the joint updating of all the check nodes of the group via a Maximum-A-Posteriori (MAP) type process, and the updating of all the first variable nodes and all the second variable nodes connected to the group except the at least one internal second variable node. The method may include iteratively repeating the updates.

Method and device for decoding LDPC encoded codewords with a fast convergence speed

This is a method for controlling the decoding of a LDPC encoded codeword composed of several digital data, said LDPC code being represented by a bipartite graph between check nodes (CN) and variable nodes (VN). Said method comprises updating messages exchanged iteratively between variable nodes (VN) and check nodes (CN). Said method comprises, at each iteration, calculating for each variable node a first sum (&#x39b;) of all the incident messages (&#x3bb;) received by said variable node and the corresponding digital data (&#x3bb;) and calculating a second sum (VNR) of all the absolute values of the first sums (&#x39b;), and stopping the decoding process if the second sum (VNR) is unchanged or decreases within two successive iterations and if a predetermined threshold condition is satisfied.

Method and device for controlling the decoding of a LDPC encoded codeword, in particular for DVB-S2 LDPC encoded codewords

The LDPC decoder includes a processor for updating messages exchanged iteratively between variable nodes and check nodes of a bipartite graph of the LDPC code. The decoder architecture is a partly parallel architecture clocked by a clock signal. The processor includes P processing units. First variable nodes and check nodes are mapped on the P processing units according to two orthogonal directions. The decoder includes P main memory banks assigned to the P processing units for storing all the messages iteratively exchanged between the first variable nodes and the check nodes. Each main memory bank includes at least two single port memory partitions and one buffer the decoder also includes a shuffling network and a shift memory.

LDPC decoder for DVB-S2 decoding

The method is for decoding an LDPC encoded codeword, the LDPC code being represented by a bipartite graph between check nodes and variable nodes including first variable nodes and second variable nodes connected to the check nodes by a zigzag connectivity. The method includes updating messages exchanged iteratively between variable nodes and check nodes including a first variable processing phase during which all the messages from the first variable nodes to the check nodes are updated and a check nodes processing phase during which all the messages from the check nodes to the first variable nodes are updated. The check nodes processing phase further includes updating all the messages from the second variable nodes to the check nodes, and directly passing an updated message processed by a check node to the next check node through the zigzag connectivity.

Method and device for decoding DVB-S2 LDPC encoded codewords

An electronic device may include a source memory device partitioned into N elementary source memories for storing a sequence of input data sets, and a processor clocked by a clock signal and having N outputs for producing, per cycle of the clock signal, N output data sets respectively associated with the N input data sets stored in the N elementary source memories at respective source addresses. The electronic device may also include N single port target memories, N interleaving tables including, for each relative source address, the number of a target memory and the respective target address thereof, N cells connected in a ring structure. Further, each cell may also be connected between an output of the processor, an interleaving table, and a target memory.

Electronic device for reducing interleaving write access conflicts in optimized concurrent interleaving architecture for high throughput turbo decoding

A method and apparatus are disclosed for decoding according to a Log-MAP algorithm, a bit sequence encoded by a convolutional encoder and received through a noisy channel. A digital signal processor (DSP) for performing the decoding is provided with an extended core possessing a transition metric calculation unit () for calculating transition metric values of the encoder trellis for output to a memory store () of the DSP, and for output to a unit () for performing a Log-MAP add-compare-select operation. The Log-MAP add-compare-select unit () calculates updated path metric values of the encoder trellis for storage in a memory store () of the DSP, and for input to a Log-Likelihood Ratio calculating unit (). The Log-Likelihood Ratio calculating unit () are each controlled by the program control unit () of the DSP, and communicate with the data memories () of the DSP, via data lines ().

Method and apparatus for decoding a bit sequence

A decoder has a first memory for storing a coded first image. The image is stored in the first memory until it has been decoded at least twice. The results of the decoding operations can be supplied to a playback device. The invention makes it possible to dispense with an output frame buffer for the decoded first image, and thus only little memory is required in the decoder.

Growing community of inventors

Queidersbach, Germany

Norbert Wehn