Infineon Technologies Ag

Infineon Technologies Dresden Gmbh

Other

Norbert Urbansky

Sven Schmidbauer

Dirk Meinhold

Jürgen Amon

Ralf Staub

Markus Fischer

Hans-Joerg Timme

Reimund Engl

Alexander Ruf

Jakob Kriz

Alfred Vater

Scott David Wallace

Bernd Schultrich

Peter Siemroth

Norbert Mais

Gerald Dallmann

Christian Wenzel

Wilhelm Claussen

Stephan Henneck

Thomas Gärtner

Wolfgang Klimes

Thomas Shuelke

Heike Rosslau

According to various embodiments, an electrode may include at least one layer including a chemical compound including aluminum and titanium.

Electrode, an electronic device, and a method for manufacturing an optoelectronic device

Embodiments relate to a method for making a semiconductor structure, the method comprising: forming a seed layer in direct contact with a dielectric material; forming a masking layer over the seed layer; patterning the masking layer to expose the seed layer; forming a fill layer over the exposed seed layer; and causing the seed layer to react with the dielectric layer to form a barrier layer between the fill layer and the dielectric layer.

Semiconductor structure and method for making same

One or more embodiments relate to a method of forming a semiconductor device, comprising: forming a structure, the structure including at least a first element and a second element; and forming a passivation layer over the structure, the passivation layer including at least the first element and the second element, the first element and the second element of the passivation layer coming from the structure.

Semiconductor structure having metal oxide or nirtride passivation layer on fill layer and method for making same

In one embodiment, a method of forming a semiconductor device includes forming a metal line over a substrate and depositing an alloying material layer over a top surface of the metal line. The method further includes forming a protective layer by combining the alloying material layer with the metal line.

Protection layers for conductive pads and methods of formation thereof

A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between the semiconductor substrate and the metal filling. The semiconductor substrate has a doped region in the contact hole.

Method for fabricating metallic bit-line contacts

A method makes contact with a doping region formed at a substrate surface of a substrate. An insulating layer is applied on the substrate surface and a contact hole is formed in the insulating layer. A metal-containing layer is subsequently deposited on the insulating layer and the surface region of the doping region that is uncovered by the contact hole. In a subsequent thermal process having two steps, first the metal-containing layer is reacted with the silicon of the doping region to form a metal silicide layer and then the rest of the metal-containing layer is converted into a metal-nitride-containing layer in a second thermal step.

Method for making contact with a doping region of a semiconductor component

A contact layer is used, for example, as a liner for the fabrication of electrical contacts in contact holes. The contact layer is fabricated in two steps, in a first step a first contact layer is deposited, in which only a small proportion of the particles to be sputtered is ionized. In a second sputtering step, a second contact layer is sputtered, in the course of whose fabrication a larger proportion of the particles to be sputtered is ionized. The procedure ensures that the first contact layer is disposed as a protective layer on the substrate by gentle sputtering before the second contact layer is sputtered.

Method for fabricating a contact layer

The invention relates to a process and a device for metallization of semiconductor structures, with which areas of the surface can be connected to be electrically conductive using strip conductors in one or a plurality of planes, and contacts between the strip conductors of different planes. The process for producing metallic coatings on semiconductor structures by depositing from a vapor phase under vacuum, in trenches produced for the strip conductors and holes for strip conductor connection in the substrate material such as SiO,or other inorganic and organic materials is characterized in that a known per se pulsed vacuum-arc evaporator is used, a barrier layer being deposited on the surface of the trenches and holes of the substrates using the plasma of the evaporator and/or the trenches and holes being filled with low-impedance strip conductor material from a further plasma of said type of evaporator. The invention describes a device for carrying out the process which can be used, along with the device, to metal-coat trenches and holes with a high aspect ratio without hollow spaces.

Process and device for production of metallic coatings on semiconductor structures

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Dresden, Germany

Norbert Urbansky