Infineon Technologies Ag

Norbert Neurohr

Andreas Menkhoff

Stefan Herzinger

Stefan Meier

Mario Steinert

Matthias Schöbinger

Ingo Feldner

A method is disclosed, including identifying a preamble in a frame, where the preamble has a preamble length 1. M data items received in succession are stored. The m data items once divided into n portions, where the data items in each portion have respectively been received at successive times and where m and n are natural numbers and the following applies to m and n: m&#x3e;n, m&#x3e;1, n&#x3e;1. The n portions are respectively correlated to the expected values to form component correlation results. Delaying the component correlation results, with at least two component correlation results being delayed by different lengths. The method also includes combining the delayed component correlation results to form a total correlation value. The total correlation value is used to determine whether the m received data items contain the preamble of a frame.

Digital receiver synchronization

A method and a device for determining an output sequence of output elements from an input sequence of input elements is provided, the method or the device being implemented according to a decision feedback equalizer. The adaptation of coefficients of the equalizer is performed on the basis of an estimated error determined as a function of a scaling (a, c0). According to the invention the scaling (a, c0) is determined such that it differs from a nominal input value by a deviation value during transmission without symbol interference. The deviation value is dependent on non-compensatable inter-symbol interference.

Method and apparatus for determining an output sequence from an input sequence

A detector for a receiver generates a clock phase detection signal and a carrier phase detection signal from of a plurality of clock polyphase signals of an oversampled signal. The detector comprises a plurality of carrier phase detectors, a plurality of variance estimation units, a selection unit and an output unit. Each phase detector determines the carrier phase of a clock polyphase signal and emits a carrier phase signal corresponding to the carrier phase. Each variance estimation unit determines the variance of one of the carrier phase signals. The selection unit compares the variances of the carrier phase signals with one another and emits a selection signal as the clock phase detection signal for selection of that clock polyphase signal whose associated carrier phase has the smallest variance. The output unit emits at least one of the carrier phase signal as the carrier phase detection signal.

Detector for clock phase and carrier phase

A circuit is disclosed that is designed to carry out add compare select operations for determination of state metrics. The circuit is also designed to carry out a computation operation which goes beyond an add compare select operation for state metric determination, wherein the circuit is either configurable for this purpose and/or has an output for emitting at least one circuit-internal variable which goes beyond the output variable from the add compare select operation.

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Neuried, Germany

Norbert Neurohr