Arm Limited

Norbert Bernard Eugéne Lataille

Richard Roy Grisenthwaite

Stuart David Biles

Frederic Claude Marie Piry

Florent Begon

Cédric Denis Robert Airaud

Nicolas Chaussade

Philippe Jean-Pierre Raphalen

Jocelyn Francois Orion Jaubert

Philippe Luc

Elodie Charra

Mélanie Vincent

Mélanie Emanuelle Lucie Vincent

A data processing apparatus and method are provided for converting data values from a first endian format to a second endian format. Swizzle circuitry is provided for receiving a block of data containing at least one data value, and for converting each data value from the first endian format to the second endian format. The swizzle circuitry comprises first swizzle circuitry for performing a re-ordering operation on the block of data assuming the at least one data value contained therein is of a first size, in order to produce re-ordered data. Second swizzle circuitry is provided which is responsive to an indication that the at least one data value is of a size different to the first size to perform an additional re-ordering operation on the re-ordered data having regard to the size of the at least one data value in order to convert each data value to the second endian format.

Data processing apparatus and method for converting data values between endian formats

A plurality of processing units for performing data processing operations require access to data in shared memory. Each has an associated cache storing a subset of the data for access by that processing unit. A cache coherency protocol ensures data accessed by each unit is up-to-date. Each unit issues a write access request when outputting a data value for storing in shared memory. When the write access request requires both the associated cache and the shared memory to be updated, a coherency operation is initiated within the cache coherency logic. The coherency operation is performed for all of the caches including the cache associated with the processing unit that issued the write access request in order to ensure that the data in those caches is kept coherent.

Handling of write access requests to shared memory in a data processing apparatus

Within a data processing system including a register renaming mechanism, register renaming for some conditional instructions which are predicted as not-executed is suppressed. The conditional instructions which are subject to such suppression of renaming may not be all conditional instructions, but may be those which are known to consume a particularly large number of physical registers if they are subject to renaming A conditional load multiple instruction in which multiple registers are loaded with new data values taken from memory in response to a single instruction is an example where the present technique may be used, particularly when one of the registers loaded is the program counter and accordingly the instruction is a conditional branch.

Suppressing register renaming for conditional instructions predicted as not executed

A data processing apparatus and method are provided for handling execution of instructions within a data processing apparatus having a plurality of processing units. Each processing unit is operable to execute a sequence of instructions so as to perform associated operations, and at least a subset of the processing units form a cluster. Instruction forwarding logic is provided which for at least one instruction executed by at least one of the processing units in the cluster causes that instruction to be executed by each of the other processing units in the cluster, for example by causing that instruction to be inserted into the sequences of instructions executed by each of the other processing units in the cluster. Such a mechanism provides a particularly efficient technique to cause each of the processing units in the cluster to perform an identical operation which can be useful in a variety of situations, for example in an SMP system where coherency of data is required and accordingly maintenance operations need to be performed periodically within each processing unit to ensure such coherency.

Execution of instructions within a data processing apparatus having a plurality of processing units

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Le Cannet, France

Norbert Bernard Eugéne Lataille