Arm Limited

Norbert Bernard Eugene Lataille

Florent Begon

Frederic Claude Marie Piry

Philippe Jean-Pierre Raphalen

Melanie Emanuelle Lucie Vincent

Stuart David Biles

Cédric Denis Robert Airaud

Luc Orion

Julie-Anne Francoise Marie Pruvost

Cache logic is provided for use in a data processing apparatus, the cache logic having a cache storage comprising a plurality of cache lines for storing data values. Control logic is arranged, in response to an access request issued by a device of the data processing apparatus identifying a memory address of the data value to be accessed, to cause a lookup operation to be performed to determine whether the data value for that memory address is stored within the cache storage. The control logic is further operable if the data value is not stored in the cache storage to perform a linefill process, the linefill process comprising performing an eviction to evict to memory of the data processing apparatus current content of a selected cache line, keeping the current content valid in the selected cache line whilst the eviction is taking place, and storing from the memory into the selected cache line new content including the data value the subject of the access request. Whilst the eviction is taking place, the control logic allows the current content of the selected cache line to be accessed by subsequent read access requests seeking to read a data value within that current content, but prevents the current content of the selected cache line being accessed by subsequent write access requests seeking to write to a data value within that current content.

Cache logic, data processing apparatus including cache logic, and a method of operating cache logic

A processorutilising register renaming executes program instructions requiring a large number of architectural register specifiers to be renamed by dividing the renaming tasks into an initial set and a remaining set. The initial set are performed first and the results passed via a main channelfor further processing. The remaining set are performed in sequence with the results being passed via a background channelfor further processing. This technique is particularly useful for performing renaming operations for load/store multiple LDM instructions.

Method for renaming a large number of registers in a data processing system using a background channel

A register renaming unit has mapping control circuitry which serves to suppress unnecessary mapping operations in dependence upon a detected current state of the data processing system. One example of circumstances which can be detected from the current state and in which mapping can be suppressed and the existing mapping reused are that in respect of the existing physically mapped register there are no pending writes, no pending reads and no pending requirement for that physically mapped register to be preserved as a recovery register. Another example of a current state in which a mapping can be reused is adjacent program instructions having mutually exclusive condition codes and sharing a destination register such that only one of those adjacent instructions will ever be executed.

Selective suppression of register renaming

A data processing apparatus processes a stream of instructions from an instruction set. The instruction set includes exception instructions and non-exception instructions. Exception instructions may cause a break in an instruction flow, and non-exception instructions execute in a statically determinable way. At least two processing blocks process instructions from the stream of instructions. A first processing block has a set of physical registers associated with it for storing data values being processed by the first processing block. Renaming circuitry associated with the first processing block maps architectural registers specified in instructions to be processed by the first processing block to physical registers within the set of physical registers. A second processing block has a set of physical registers associated with it for storing data values being processed by the second processing block. The second processing block and registers do not support renaming. Control circuitry identifies exception instructions in the instruction stream and detects when the exception instructions have been committed. The second processing block receives signals from the control circuitry and suspends processing of an instruction in the second processing block until all preceding exception instructions have been committed.

Data processing apparatus for processing a stream of instructions in first and second processing blocks with the first processing block supporting register renaming and the second processing block not supporting register renaming

A data processing apparatussupports out-of-order processing register renaming using a renaming stage. A set of physical registersis mapped to architectural registers. Available-register identifying logicis used to identify which physical registersare available for use by the renaming stage. The available-register identifying logicincludes an instruction FIFOstoring register mapping data for unresolved instructions and indicating physical registersstoring data values which may be required in association with those unresolved speculative instructions. The speculative instructions may be predicted branch instructions, load/store instructions, conditional instructions or other types of instruction.

Determining register availability for register renaming

A data processing systemutilizes a register renaming mechanismto rename architectural register specifiers to physical register specifiers to facilitate out-of-order processing. The register renaming mechanismincludes a renaming recovery unitwhich enables recovery from incorrectly executed speculative instructions by restoring the register mapping to the state prior to those incorrect instructions with the physical registers restored to containing the data values which were current at the time prior to that incorrect instruction. In the case of load instructions, these are treated as speculative but the data value returned in response to the load instruction and stored within a physical register is released for use as soon as it is returned and prior to a determination result being available as to whether or not that data value is corrupt. Corruption checking an take the form of ECC checking, parity checking and the like, and when a late error signal is generated then this indicates whether or not the data value has been properly released for use. If corruption is detected, then the renaming recovery unitis used to recover the state of the systemin a precise way to that preceding the failing load instruction.

Speculative data value usage

Within a coherent multi-processing system multiple processor coresare coupled via respective memory buses to a memory access control unit. The memory buses are formed of a uni-processing portion containing signals specifying a memory access request in accordance with a uni-processing protocol. This uni-processing bus is augmented by a multi-processing bus containing signals giving additional information concerning memory access requests which may be used by the memory access control unit to service those requests and manage coherency within the system.

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Le Cannet, France

Norbert Bernard Eugene Lataille