Broadcom Corporation

Marvell Asia Pte., Ltd.

Nong Fan

Hongtao Jiang

Tuan Hoang

Keh-Chee Jen

Geoffrey O Hatcher

Ray Luan Nguyen

Morteza Azarmnia

Dawood Alam

A high-speed data receiver includes interleaver circuitry configured to divide a received data stream into a plurality of interleaved paths for processing, spectral content detection circuitry configured to derive spectral content information from data on each of the plurality of interleaved paths, sorting circuitry configured to bin the derived spectral content information according to energy levels, stream attribute determination circuitry configured to determine, based on sorted spectral content, one or more of path offsets of the interleaved paths, gain mismatch among interleaved paths, signal bandwidth mismatch and pulse width mismatch, and equalization circuitry configured to correct the one or more of the determined offsets, the determined gain mismatch and the determined signal width mismatch. Equalization circuitry may be configured to equalize a gain-normalized signal by separately adjusting respective bandwidth actuators of each respective interleaved path and respective pulse width actuators of each respective interleaved path.

Spectral content detection for equalizing interleaved data paths

A system () includes a communication path () and transmits data on a network (). A transmitter () transmits data on the network and a receiver () receives data from the network. A component () in the communication path has a transfer characteristic (C, C, C) adjusted in response to errors in data transmitted over and received from the network in order to reduce the error rate.

Bit error rate based system and method for optimizing communication system performance

A method and system for evaluating performance of a device by on-chip determination of BER may include establishing and generating PRBS test packets in a closed communication path internally within a physical layer device (PLD) and a remote PLD. A BER for the PLD may be determined from within the PLD based on a comparison of at least a portion of the generated test packets with at least a portion of the generated test packets transmitted over the closed communication path received by the PLD via the closed communication path from the remote PLD. A transmit path of the PLD may be internally coupled to a receive path of the PLD, and a receive path of the PLD may be internally coupled to a transmit path of the PLD. The PLD may be internally configured to operate in an internal optical loopback mode or an internal electrical loopback mode.

System and method for determining on-chip bit error rate (BER) in a communication system

A test packet generator () within a physical layer device () may generate test packets to be communicated over a closed communication path established within the physical layer device (). The test packets may include a pseudo-random bit sequence. A receiver within the physical layer device () may receive at least a portion of the generated test packet. A test packet checker () within the physical layer device may compare at least a portion of the received test packets with at least a portion of the generated test packets in order to determine the bit error rate for the physical layer device. A window counter () within the physical layer device () may count at least a portion of a number of bits received within the generated test packets and a number of bits that are in error in at least a portion of the number of bits received. Accordingly, the bit error rate may be calculated based on a ratio of the number of counted bits in error to the number bits counted in the at least a portion of the number of bits received.

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Nong Fan