Hynix Semiconductor Inc.

Hyundai Electronics Industries Co. Ltd.

Noh Yeal Kwak

Sang Wook Park

Byung Hee Cho

Dong Ho Lee

Jung Ho Lee

Cha Deok Dong

In Seok Yeo

Min Sik Jang

Sahng Kyoo Lee

Hong Seon Yang

Jeong Hwan Park

Seung Chul Lee

Chul Young Ham

This invention relates to a method of fabricating a semiconductor device. A P well for a cell junction may be formed by performing an ion implantation process employing a zero tilt condition. Stress caused by collision between a dopant and a Si lattice within a semiconductor substrate may be minimized and, therefore stress remaining within the semiconductor substrate may be minimized. Accordingly, Number Of Program (NOP) fail by disturbance caused by stress remaining within a channel junction may be reduced. Further, a broad doping profile may be formed at the interface of trenches by using BFas the dopant when the P well is formed. A fluorine getter layer may be formed on an oxide film of the trench sidewalls and may be used as a boron diffusion barrier. Although a Spin On Dielectric (SOD) insulating layer may be used as an isolation layer, loss of boron (B) may be prevented. Accordingly, an additional ion implantation process for compensating for lost boron (B) may be omitted and a NOP disturbance characteristic may be improved.

Method of fabricating semiconductor device

A method of forming an isolation structure of a semiconductor device includes implanting dopants of a first type into a semiconductor substrate to form a doped region in the substrate. A mask layer is provided over the substrate and the doped region of the substrate. The mask layer is patterned to expose an isolation region of the substrate, the isolation region defining an active region, the isolation region and the active region being defined at least partly within the doped region. Dopants of a second type are implanted at an edge of the active region as defined by the isolation region. The isolation region of the semiconductor substrate is etched to form an isolation trench having a depth that extends below a depth of the doped region. Dopants of a third type are implanted on sidewalls of the trench in order to minimize the dopants of the second type provided on the sidewalls of the isolation trench from migrating away from the sidewalls. The trenches are filled with a dielectric layer to form an isolation structure.

Method of forming isolation layer of semiconductor device

Disclosed is a method for manufacturing a flash memory cell. A structure in which a floating gate, an ONO dielectric film and a control gate are stacked is formed by means of a gate mask process and an etch process. After a rapid thermal nitrification process is performed, a re-oxidization process is performed. Therefore, Si-dangling bonding broken during the gate etch process becomes a Si&#x2014;N bonding structure by means of a rapid thermal nitrification process. As such, as abnormal oxidization occurring at the side of an ONO dielectric film during a re-oxidization process is prohibited, a smiling phenomenon of the ONO dielectric film is prevented.

Method for manufacturing flash memory cell

Disclosed is a method of manufacturing semiconductor devices. Before the threshold voltage ion is implanted, an inert ion having no electrical properties is implanted into the bottom of a channel region to form an anti-diffusion layer. Therefore, it is possible to prevent diffusion of an ion for adjusting the threshold voltage into the bottom of the channel region, occurring in a subsequent annealing process, and prohibit behavior of the ion at the channel region when a high voltage is applied to a P well. Further, the anti-diffusion layer serves as a layer to gather defects, etc. existing in the semiconductor substrate. Also, as the amount of channel ion could be adjusted by controlling the implantation depth of the inert ion, it is possible to control the threshold voltage of the device depending on higher integration.

Method of manufacturing semiconductor devices

Disclosed is a method of manufacturing a semiconductor device. A monoatomic dopant having a high atomic weight is implanted to form an ion implantation layer, instead of using a dopant of a small atomic weight such as B or a molecular ion such as a BFin order to control the threshold voltage of the semiconductor device. Therefore, in an annealing process for mitigating damage caused by ion implantation, it is possible to limit TED (transient enhanced diffusion) of the dopant and prevent degradation of the film quality due to outgasing.

Method of manufacturing flash memories of semiconductor devices

Disclosed is a method of manufacturing a semiconductor device. In ion implantation process for controlling the threshold voltage of the transistor or the semiconductor device such as a flash memory cell, the dose of the impurity capable of securing the uniformity is implanted by minimum. The retained dose of the impurity is controlled by out gassing the implanted impurity by means of a cleaning process. Therefore, a uniform distribution characteristic of the implanted impurity could be obtained. A transistor or a flash memory cell of a low operating voltage could be manufactured.

Method of manufacturing a semiconductor device

A method of manufacturing a semiconductor device is disclosed which comprises, forming a first well region by performing an ion implantation process for implanting first ions into a semiconductor substrate, and then forming a second well region in the first well region by performing an ion implantation process for implanting second ions having larger mass than the first ions; and forming a three-part or three-fold well region by performing an annealing process on the result structure wherein the lighter first ions are disposed in the upper and lower well regions and the heavier second ions are disposed in the middle well region. Therefore, it is possible to prevent TED phenomenon generated due to the high-energy heat treatment process to be performed later and to provide the increased activation ratio of ions compared to the conventional source/drain region in which only the ions having large mass are implanted by performing an annealing process after the first well region and the second well region are formed.

Method of manufacturing semiconductor device

Disclosed is a method of manufacturing a semiconductor wafer. In the present invention, a nucleation site is formed in a region deep into the wafer through low-temperature annealing process, and oxygen or precipitation material, the metallic impurity, or the like is trapped in the nucleation site through rapid thermal annealing process. As a gettering effect is improved using the rapid thermal annealing process, the concentration of the impurity on the surface of the wafer can be lowered and the reliability of the device could be improved. Further, the annealing steps can be reduced than the prior art and the productivity of the device can thus be increased.

Method of manufacturing a semiconductor wafer

The present invention relates to a method of forming a high voltage junction in a semiconductor device. The method includes forming a double diffused drain junction, and making amorphous the double diffused drain junction to a first depth by implanting an impurity having a high atomic weight than an impurity injected into the double diffused drain junction, implanting an impurity so that the concentration of the concentration of an impurity to a second depth lower than the first depth and then activating the impurities. Thus, the present invention can reduce the sheet resistance by prohibiting diffusion of an impurity, prohibit a channeling phenomenon by lowering the depth of the junction, and remove crystal defects by sufficiently activating an impurity and since a subsequent annealing process for activation can be performed at a high temperature, and thus improve reliability of a process and an electrical characteristic of the device.

Method of forming high voltage junction in semiconductor device

A method of manufacturing a flash memory device, in which a spike annealing is performed after an ion implantation for controlling a threshold voltage. Therefore, it is possible to obtain a uniform and stabilized doping profile for controlling a threshold voltage, to use BFions as a dose for controlling a threshold voltage to obtain a shallow channel junction, to obtain different doping profiles in the channel junction depending on the process conditions and the atmosphere in the spike annealing equipment, and to control a doping profile for controlling a threshold voltage.

Method of manufacturing flash memory device

Disclosed is a method of forming an isolation film in semiconductor devices using a shallow trench. Trenches are formed in silicon substrates of a memory cell region and a peripheral circuit region. The inert ion is then injected into the surface of the trench in the peripheral circuit region, thus forming an amorphous layer. Thereafter, an oxidization process is implemented so that a thick oxide film is grown due to excessive oxidization at the amorphous layer, thus making thicker the trench in the peripheral circuit region than the trench in the memory cell region by a thickness of the oxide film.

Method of forming an isolation film in a semiconductor device

The present invention relates to a method of manufacturing a flash memory cell. The method includes forming a stack gate in which a floating gate and a control gate are stacked at a given region of a semiconductor substrate, and performing a rapid thermal nitrification process to form a nitride film at the side of the stack gate and over the semiconductor substrate. Therefore, the present invention can improve a retention characteristic and can prevent movement of threshold voltage control ions.

Method of manufacturing a flash memory cell

Disclosed is a method of manufacturing a semiconductor memory device. An ion implantation layer is formed into a given depth of the semiconductor substrate. Therefore, it is possible to prevent the dopant (P31) gettered on the surface of the semiconductor substrate from being diffused toward the bottom when a well ion is injected. The dopant (P31) gettered on the surface of the semiconductor substrate is easily experienced by transit-enhanced diffusion even at low temperature. Also, the dopant may serve as counter dopping in the buried channel. In the present invention, as the behavior of this dopant (P31) is prohibited in a subsequent annealing process, the concentration of the ion for controlling the threshold voltage could be uniformly kept. Therefore, the present invention can manufacture devices of high reliability having a stable threshold voltage characteristic and can be flexibly applied to manufacturing the devices depending on reduction in the design rule.

Method of manufacturing a semiconductor memory device

A method of manufacturing a flash memory device includes the steps of sequentially forming a tunnel oxide film and a first polysilicon layer on a semiconductor substrate in which a device separation film is formed and then patterning the tunnel oxide film and the first polysilicon layer to form a floating gate; forming a mask so that a portion in which a source region will be formed can be exposed and then removing the device separation film at the exposed portion; forming a dielectric film including a lower oxide film, a nitride film, and an upper oxide film on the entire structure; performing an annealing process; then forming a second polysilicon layer on the dielectric film; sequentially removing the polysilicon layer, the upper oxide film, and the nitride film in a portion in which a source region and a drain region will be formed, and injecting impurity ions into the semiconductor substrate at a portion in which the lower oxide film remains to form a source region and a drain region; after removing the remaining lower oxide film, sequentially forming a third polysilicon layer and a tungsten silicide layer on the entire structure and then patterning the third polysilicon layer and the tungsten silicide layer to form a control gate; and performing an annealing process for activating the impurity ions injected into the source region and the drain region.

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Ichon-shi, South Korea

Noh Yeal Kwak