Skhynix Inc.

Hynix Semiconductor Inc.

Noh-Jung Kwak

Do-Hyung Kim

Seung-Bum Kim

Dae-Sik Park

Se-Han Kwon

Chang-Youn Hwang

Hong-Gu Yi

Yun-Je Choi

Ki-Soo Choi

Doo-Sung Jung

Seung-Jin Yeom

Jong-Han Shin

Myung-Ok Kim

Sun-Hwan Hwang

Jum-Yong Park

Cheol-Hwi Ryu

Chang-Heon Park

Yong-Soo Choi

Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.

Semiconductor device including air gaps and method for fabricating the same

A semiconductor device includes first conductive patterns adjacent to each other and isolated by a trench including first and second trenches, a second conductive pattern formed in the first trench, and an insulating pattern partially filling the second trench under the second conductive pattern and formed between the first conductive patterns and the second conductive pattern.

Semiconductor device with damascene bit line and method for manufacturing the same

A method for fabricating a semiconductor device includes sequentially stacking a pad oxide layer and a hard mask layer over a substrate, forming a device isolation layer over the substrate, forming a capping layer pattern configured to open a first region of the substrate and cover a second region of the substrate, removing the hard mask layer, removing the capping layer pattern, and removing the pad oxide layer.

Method for fabricating semiconductor device with buried gates

A method for fabricating a semiconductor device through a chemical mechanical polishing (CMP) process is provided. The CMP process is performed by using a slurry. The semiconductor device fabrication method can ensure the reliability and economical efficiency of the device by performing a CMP process using a CMP slurry having a high polishing selectivity with respect to a target surface, an anti-scratch characteristic, and a high global planarization characteristic.

Method for fabricating semiconductor device

Growing community of inventors

Gyeonggi-do, South Korea

Noh-Jung Kwak