Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Noga Deshe

Yehuda Hahn

Gadi Vishne

Vered Kelner

Alexander Bazarsky

Abhijeet Manohar

Daniel Edward Tuers

Karin Inbar

Michael Micha Ionin

Sebastien Andre Jean

Itay Busnach

Ilya Gusev

Yevgeny Zagalsky

Yan Nosovitsky

Alon Banin

Eran Ben Abou

Nurit Appel

Lilia Brechman

Yaron Zamir

A method and apparatus for dynamic controller buffer management is disclosed. According to certain embodiments, responsive to commands received from a host, a controller may adjust one or more partitions of a controller buffer memory to adjust the size of different types of buffer memory. In some embodiments, preset buffer memory configurations may be applied to the buffer memory to adjust buffer memory allocation based on the current workload. By way of example, when sequential reads are detected, a TRAM buffer size may be increased to provide additional RLA buffers, at the expense of XRAM and/or L2P buffer size. Where operations involving SLC memory is detected, allocation of buffer memory parity buffers of XRAM may be decreased, to provide additional buffer space to L2P.

Dynamic controller buffer management and configuration

A data storage device includes a memory device, a random access memory (RAM) device, and a controller coupled to the memory device and the RAM device. The controller is configured to determine a workload type of the data storage device, determine to store at least a portion of a compressed logical to physical translation table (ZCAT) in the RAM device based on the workload type, and utilize a remaining portion of the RAM device to perform background operations. The controller is further configured to determine a persistence or temperature of the ZCAT, where the portion of the ZCAT stored to the RAM device is based on the persistence and/or the temperature of the ZCAT. The remaining portion of the ZCAT is stored in the HMB, where the remaining portion may update any out-of-date ZCAT entries.

Storage optimization of CAT table during background operations

Exemplary methods and apparatus are disclosed to select data evacuation policies for use by a solid state device (SSD) to relocate data from an upper (high performance) memory tier to a lower memory tier. The upper tier may be, e.g., a single-layer cell (SLC) tier of a multi-tier NAND memory, whereas the lower tier may be, e.g., a triple-layer cell (TLC) or a quad-level cell (QLC) tier of the NAND memory. In one example, the SSD monitors its recent input/output (I/O) command history. If a most recent command was a read command, the SSD performs a 'lazy' evacuation procedure to evacuate data from the upper tier storage area to the lower tier storage area. Otherwise, the SSD performs a 'greedy' or &#x201c;eager&#x201d; evacuation procedure to evacuate the data from the upper tier to the lower tier. Other evacuation selection criteria are described herein based, e.g., upon predicting upcoming I/O commands.

Tiered storage data evacuation within solid state devices

A system and method is disclosed for managing a non-volatile memory system having a multi-processor controller. The controller may be configured with a plurality of processors and a shared data queue in a cyclic data buffer. Each of the plurality of processors may manage a separate pointer pointing to a different entry of the shared data queue and multiple ones of the processors may concurrently access or update entries in the shared data queue.

Multi-processor non-volatile memory system having a lockless flow data path

A storage device utilizing read look ahead (RLA) may utilize auxiliary or spare latches as a RLA cache for storing pre-fetch data. The RLA may predict the next commands and do a speculative read to the flash using the latches for RLA storage. The auxiliary/spare latches may be present on a plane or die of non-volatile memory and may be different from the transfer data latch (XDL) that transfers data from the memory and the host. When the XDL is backed up, sense commands may still be performed and the data is stored in the auxiliary latches before being transferred with the XDL.

Preserving read look ahead data in auxiliary latches

A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured to receive a first command from an access device, the first command associated with a first logical block address (LBA). The controller is also configured to, after receiving the first command, receive a second command and a third command from the access device. The second command is associated with a second LBA that precedes the first LBA, the third command is associated with a third LBA that succeeds the first LBA. The controller is further configured to determine that the first command, the second command, and the third command correspond to a sequential command stream.

Detection of a sequential command stream

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Raanana, Israel

Noga Deshe